View AMG-XB404_4770658.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

AMG-XB404 fully integrated single motor controller for electrical motors 1. functional description of the AMG-XB404 the AMG-XB404 is a feature rich soc, providing a single chip solution for motor control, including digital motor control engine (dmce), power factor correction (pfc), high level system control mcu, and switch mode power supply (smps). the ic's multi-core design enables parallel execution of all system functions while keeping the mcu load to a minimum. the dmce include s a processing unit, pwm generator, and power stage driver allowing for sensorless drive. the amg- xb404 's switching power supply circuit, which includes software adjustable switching frequency, requires the ic to only have a single , low-grade power supply. 2. features ? supply voltage: 4.5vdc...5.5vdc ? soc for asynchronous & synchronous motors ? independent dmce , pfc, mcu, smps ? avr compatible 8 bit mcu with 32kb program memory ? over-current protection with single shunt current control ? fully digital, programmable pfc controller ? internal 2% rc-oscillator ? built-in oscillator for external crystal or resonator (optional) ? software-adjustable clock frequency fll ? 10-bit 2-msps multiplexed adc ? integrated switching power supply (smps) ? integrated eeprom memory ? 17 gpio ( 3 thereof which can be analog) ? ambient temperature range: -25c...85c ? package: lqfp68 C body size: 10 mm x 10 mm x 1.4mm ? rohs compliant AMG-XB404 revision: a 2. nov. 2012 ? all rights reserved page 1 of 73
AMG-XB404 fully integrated single motor controller for electrical motors 3. application AMG-XB404 revision: a 2. nov. 2012 ? all rights reserved page 2 of 73 figure 1 : AMG-XB404 simplified application circuit 15v t gnd 5v drv 15v drv ac hvdc digital pfc avr comp. mcu adc smps spi uart twi power stage m 15v gnd vdc AMG-XB404 digital motor control engine eeprom 15v 5v
AMG-XB404 fully integrated single motor controller for electrical motors table of contents 1. functional description of the AMG-XB404 ................................................................................... 1 2. features ....................................................................................................................................... 1 3. application .................................................................................................................................... 2 4. block diagram .............................................................................................................................. 6 5. block descriptions ........................................................................................................................ 7 5.1. system spi unit and on-chip bus ................................................................................................. 7 5.2. io expander .................................................................................................................................... 9 5.2.1. ic revision information ................................................................................................... 9 5.2.2. test modes, eeprom self-programming mode, lock indicator, clock control .............. 9 5.2.3. power output polarity and over-current flag control for dmce .................................... 9 5.2.4. switching controller pwm frequency ........................................................................... 10 5.2.5. polarity of the pfc switching signal ............................................................................. 10 5.2.6. pwm frequency setting for dmce ............................................................................... 10 5.2.7. fll configuration and status ........................................................................................ 10 5.2.8. u, v, w phase feedback monitor ................................................................................. 10 5.2.9. adc offset calibration data .......................................................................................... 11 5.2.10. pfc, dmce and adc software controlled reset signals .......................................... 11 5.2.11. operational amplifier power down signals .................................................................. 11 5.2.12. spi unit low-pass filter settings ................................................................................ 11 5.2.13. assignment of power outputs and high voltage read-back pins ............................... 11 5.2.14. dmce and pfc driver signal read-back .................................................................. 12 5.2.15. band gap reference tuning setting ........................................................................... 12 5.2.16. ofi direct read-back ................................................................................................. 12 5.2.17. eeprom direct access .............................................................................................. 12 5.2.18. mcu-accessible engineering mode enable ................................................................ 12 5.2.19. adc tun mode, dmce value offset selection .......................................................... 12 5.2.20. adc sample triggers for test, supply voltage, and temperature ............................... 12 5.2.21. io expander overview ................................................................................................ 13 5.2.22. interrupt controller ...................................................................................................... 14 5.2.23. status register ........................................................................................................... 16 5.3. analog data aquisition unit (adaq) ............................................................................................. 16 5.3.1. adc interface ................................................................................................................ 16 5.3.2. analog input signal ranges .......................................................................................... 17 AMG-XB404 revision: a 2. nov. 2012 ? all rights reserved page 3 of 73
AMG-XB404 fully integrated single motor controller for electrical motors 5.3.3. triggering analog signal acquisition ............................................................................. 18 5.3.4. accessing adc sample data, adc interrupts ............................................................... 19 5.4. digital motor control engine (dmce) ........................................................................................... 21 5.4.1. motor control processing unit (mcpu) ......................................................................... 22 5.4.2. register file .................................................................................................................. 23 5.4.3. pwm unit ...................................................................................................................... 23 5.4.4. accessing the dmce via the on-chip bus .................................................................... 24 5.4.5. power stage over-current protection ........................................................................... 26 5.5. power factor correction controller (pfc) .................................................................................... 27 5.5.1. pfc instruction set description .................................................................................... 29 5.5.2. pfc data memory description ...................................................................................... 30 5.5.3. accessing the pfc controller via the on-chip bus ....................................................... 33 5.6. switch mode power supply (smps) ............................................................................................. 35 5.7. micro controller unit (mcu) .......................................................................................................... 37 5.7.1. programming and debug interface ............................................................................... 37 5.7.1.1. program memory initialization ................................................................................ 38 5.7.1.2. shadow sram reads and writes .......................................................................... 39 5.7.1.3. eeprom rads and writes .................................................................................... 39 5.7.1.4. march c- sram test .............................................................................................. 42 5.7.1.5. eeprom calibration and user data space ........................................................... 42 5.7.1.6. debug interface ...................................................................................................... 44 5.7.2. general purpose input output interface (gpio) ........................................................... 44 5.7.3. universal asynchronous receiver transmitter interface (uart) .................................. 47 5.7.4. serial parallel interface (spi) ........................................................................................ 48 5.7.5. two wire interface (twi) .............................................................................................. 49 5.7.6. general purpose timers ............................................................................................... 52 5.7.7. watchdog timer ............................................................................................................ 53 5.8. system clock ................................................................................................................................ 55 5.9. power-on and system reset ........................................................................................................ 56 5.10. on-chip bus register summary ................................................................................................. 58 5.11. mcu instruction set .................................................................................................................... 59 6. pinning ....................................................................................................................................... 65 7. absolute maximum ratings ........................................................................................................ 66 8. electrical characteristics ............................................................................................................ 67 8.1. operational range ........................................................................................................................ 67 AMG-XB404 revision: a 2. nov. 2012 ? all rights reserved page 4 of 73
AMG-XB404 fully integrated single motor controller for electrical motors 8.2. dc characteristics ........................................................................................................................ 67 8.3. ac characteristics ......................................................................................................................... 68 8.4. adc characteristics ...................................................................................................................... 68 8.5. supply current characteristics ..................................................................................................... 69 8.6. logic-level characteristics ........................................................................................................... 69 9. ic-package ................................................................................................................................. 70 10. ic-marking ................................................................................................................................ 71 11. packing specification ................................................................................................................ 71 12. notes and cautions .................................................................................................................. 72 12.1. esd protection ............................................................................................................................ 72 12.2. storage conditions ...................................................................................................................... 72 13. disclaimer ................................................................................................................................. 72 14. contact information .................................................................................................................. 73 AMG-XB404 revision: a 2. nov. 2012 ? all rights reserved page 5 of 73
AMG-XB404 fully integrated single motor controller for electrical motors 4. block diagram AMG-XB404 revision: a 2. nov. 2012 ? all rights reserved page 6 of 73 figure 2 : AMG-XB404 block diagram m0i pfc_pwm portb[0:7] dvdd a5v vref agnd m0ifb reset unit vac pfci pfcifb o n - c h i p b u s io expander supply & ref. scs sclk sdo sdi system spi swi swv swvref smps switch mode power supply dgnd avdd m0o1 m0o2 m0o3 m0o5 m0o6 m0o4 m0r1 m0r2 m0r3 bus if m0ofi program memory pfc controller portc[2:7] . . . int data memory 16 bit risc core adc if adc vdc adc0-2 porte[0:2] bus if program memory dmce 0 pwm register file mcpu lfsr pwm measuring amplifier vco/ cxo/ rco/ fll int divider clock dmce 1 swdrv swvfb swvdd pfc controller dmce 0 pll reset mux npor nresin nresout clksel clkio xo xo_osel d5v system reset adaq program-/ debug- interface data sram risc core timers 2x 8bit 1x 16bit twi gpio block uart spi int int . . . interrupts int eeprom reset int watch- dog timer shadow prog sram int mcu
AMG-XB404 fully integrated single motor controller for electrical motors 5. block descriptions 5.1. system spi unit and on-chip bus on-chip communication is built around an 8 bit on-chip bus. there are two bus masters: the mcu core is the primary bus master and the system spi unit is the secondary bus master. the system spi unit is used to program, configure, and debug the AMG-XB404 . an activity signal from the mcu to the system spi unit indicates activity on the bus, and ensures that the system spi can only access the bus if the mcu is not. mcu bus reads and writes can slow down but not inhibit the execution of system spi commands. note that the eeprom and debug interface can be accessed via the system spi only. there are four basic system spi commands to write and read data, table 1 shows an overview. see table 32 on page 58 for an overview of all 8 bit buses addresses. command description 0 not used 1 write 8 bit data to 5 bit addressed register (see figure 1 ) 2 read 8 bit data from 5 bit addressed register (see figure 2 ) 3 write 8 bit data to 5 bit addressed register; wait for lsb=0 at the same address (see figure fehler: referenz nicht gefunden ) 4 read 32 bit data from 5 bit addressed register (see figure fehler: referenz nicht gefunden ) table 1 : system spi commands the bus employs 6 bit wide addressing. while the mcu may access all 64 addresses, the system spi can only access the 32 lower addresses. system spi transmissions are framed by the chip select signal scs, the system spi unit is active only when scs is low. the transmission timing is determined by the serial clock signal sclk. data is received via the serial data input signal sdi and sent via the serial data output signal sdo. data signals are valid at the rising edge of the serial clock signal. every transmission starts with the msb and ends with an inverted xor parity bit generated over all previously sent bits. if the transmission is received correctly, i.e. ends with a valid parity bit, the command will be processed by the system spi unit. handshaking is accomplished by the master waiting for sdo to become high after issuing a command. in case of an unsuccessful parity check sdo will stay low permanently and a time-out mechanism must take effect on the masters side. the signal AMG-XB404 revision: a 2. nov. 2012 ? all rights reserved page 7 of 73 figure 3 : spi bus masters and clients overview ... scs sdi bus activity sdo risc core prog/debug interface system spi ... sclk 8 bit on-chip bus shadow sram eeprom mcu
AMG-XB404 fully integrated single motor controller for electrical motors waveforms for all commands are shown below. a digital low-pass filter function can be activated for all inputs of the system spi unit in order to improve noise rejection, see also section 5.2 p. 9 . the maximum usable clock frequency of the system spi unit will be reduced as the filter depth is increased. the 8 bit write command contains 3 command bits followed by the 5 bit address of the register to be written to and 8 bits of data (see figure 4 ). the 8 bit read command requests the content of a register. the system spi responds by setting sdo to high when data is ready and returning 8 bits of data starting with the second negative edge of sclk (see figure 5 ). command 3 writes 8 bits of data into a register and will not return a ready status until the lsb of the previously written register becomes 0. this command is used when synchronization with units running at a different clock frequency, such as the dmce core , is required (see figure 6 ). command 4 reads a 32 bit dmce data register value in a single transmission cycle which allows for higher effective data rates than using a series of 8 bit reads and writes, see section 5.4.4 p. 24 for the description of dmce register reads. as shown in figure 7 a 5 bit dmce base address and an 8 bit register address r[7:0] are sent by the master and a 32 bit wide reply is returned by the system spi unit. AMG-XB404 revision: a 2. nov. 2012 ? all rights reserved page 8 of 73 figure 4 : command 1, write (8 bit) rdy c[2] scs sdi sdo sclk d[7] c[0] c[1] a[4] p a[0] d[0] figure 5 : command 2, read (8 bit) rdy c[2] scs sdi sdo sclk p a[0] d[0] c[0] c[1] a[4] p d[7] figure 6 : command 3, write/read (8 bit) rdy c[2] scs sdi sdo sclk d[7] c[0] c[1] a[4] p a[0] d[0]
AMG-XB404 fully integrated single motor controller for electrical motors 5.2. io expander the io expander module serves to provide additional mcu configuration registers (see table 2 ). the address register ioexpa is used to set the index for the configuration register accessed through the data register ioexpd. ioexpd provides access to to following functions. 5.2.1. ic revision information address 0 contains the number of the current AMG-XB404 revision. 5.2.2. test modes, eeprom self-programming mode, lock indicator, clock control bit 0 of address 1 enables the digital test mode if set to 1 and cannot be read. the digital test mode can only be left by performing an ic reset. this function is used during ic test only. bit 1 of address 1 sets and indicates eeprom self-programming mode which is used to write and read from the AMG-XB404 's program eeprom. eeprom self-programming mode is enabled by setting eme to 1, and left by setting eme to 0. this mode is only available when the AMG-XB404 is not locked. for details on self-programming see section 5.7.1 p. 37 . bit 2 of address 1 indicates if the AMG-XB404 is locked, 1 indicates a locked ic, which is the initial state. see section 5.7.1 , p. 37 for the details of unlocking the ic. bit 3 of address 1 is reserved and must not set to 1. bit 4 of address 1 is used to control the output of the system clock via the clkio pin. when this clkoff flag is set to 1 output via pin clkio will be disabled, e.g. when the AMG-XB404 's system clock need not be provided to off-chip circuitry. initially clkoff is set to 0. bit 5 of address 1 is used to fix the clock select signals in the present state. when this clklock flag is set to 1 the clock selection will be fixed according to the value present at pins clksel and xo_osel, see also section 5.8. page 55 , i.e. noise present at these pins will not interfere with the clock source selection. initially clklock is set to 0. 5.2.3. power output polarity and over-current flag control for dmce the lower nibble of address 2 controls the logic level at power output pins. all six signal pins will remain in high ohmic state unless dmce0oe is set to 1. if dmce0pol is set to 1 the connected power stage must have an inverting input to output characteristic, otherwise the power stage must be non-inverting. the higher nibble of address 2 controls the power stage over-current protection interface, see also figure 14 on page 26 . ofipol0 selects the polarity of the ofi signal, for an active-high ofi signal input these flags must be set to zero. ofierr0 is set to one if an over-current error of the associated power stage is encountered. if either flag is set the shared dmce/pfc interrupt flag will be set. the error flag can be reset by writing a value of 1 to ofires0 . resetting the error flag is mandatory when the shared dmce/pfc interrupt is enabled, see also section 5.2.22 p. 14 . AMG-XB404 revision: a 2. nov. 2012 ? all rights reserved page 9 of 73 figure 7 : command 4, register read (32 bit) rdy c[2] scs sdi sdo sclk p r[0] d[0] c[0] c[1] r[7] p d[31] a[0] a[4]
AMG-XB404 fully integrated single motor controller for electrical motors 5.2.4. switching controller pwm frequency the clock pre-scaler swcpre for the smps is set using addresses 3 and 4. the lower byte has to be written before the high byte. for the changed value to have an effect both bytes have to be written. the smps clock frequency is calculated as: f swc = f mcu 2 ? swcpre 1 , 1 swcpre 32767 . setting swcpre to 0 enables an internal rc oscillator to generate the smps's pwm clock. its typical frequency is 22khz. this is the default on startup. 5.2.5. polarity of the pfc switching signal the lsb of address 5 sets the polarity of the pfc controllers logic level pwm output. 0 means active high, 1 means active low. 5.2.6. pwm frequency setting for dmce dmces pwm clock setting is controlled through a register pair c1, c2 (accessible via addresses 6 to 8). the range of c1 is 0..7 (3 bit) and the range of c2 is 0..255 (8 bit). the dmce has got an individual pair of registers allowing independent pwm clocks. address 6 also holds two flags, cnt0x2 and cnt1x2, to double the pwm base frequency of the dmce. the pwm frequency can be calculated as: f pwm = { f fpu ? 2 8 ? c2 c1 2 13 ? 2 8 c1 c2 ? 1 ? 2 cntx2 ; for c2 1 f fpu ? 2 8 ? c2 2 21 ? c2 ? 2 cntx2 ; for c2 1 5.2.7. fll configuration and status fll related functions are controlled using addresses 9,10, and 12. the lower byte of the divider setting (address 9) has to be written before the high byte (address 10). the fll divider flldiv is used to set the clock frequency of the pfc, adc, and dmce which can be calculated as: f vco = flldiv 1 16 ? t rc , where t rc is the rc-ramp's rise time. the mcus clock frequency is calculated as: f mcu = f vco 8 . on reading flldiv the most recently acquired vco frequency counter value will be returned, thus allowing to monitor the vco frequency directly, note that the high byte and low byte of the counter value are not guaranteed to belong to the same vco frequency counter value. prec determines the fll's frequency step for regulating the system clock frequency. vaild values are 4 to 11. larger values correspond to smaller frequency steps. prec is increased when the target frequency is crossed within 3 frequency adjustment steps otherwise prec will be decreased. the maximum value of prec is given by the value of mprec. both maximum prec value and current prec value can be read from address 12. mprec may also be set, its initial value is 10. 5.2.8. u, v, w phase feedback monitor the comparator result of the signals present at m0r1, m0r2, and m0r3 can be read back from address 13. ru, rv, and rw are assigned according to the setting detailed in section 5.2.13. . writing bit 3, dtc0ovr, disables hardware dead time compensation for dmce0. AMG-XB404 revision: a 2. nov. 2012 ? all rights reserved page 10 of 73
AMG-XB404 fully integrated single motor controller for electrical motors writing dtc0rng sets up the allowable error range for dead time compensation of dcme0. if the actual duty cycle, determined by the feed back pins, differs from the expected duty cycle by more than 2 ( dtc0rng + cnt0x2 ) 8 , dead time compensation will be skipped. see also section 5.2.6 on page 10 for explanation on cnt0x2 . 5.2.9. adc offset calibration data addresses 14 to 25 hold the adc offset compensation values. the order of the channels is described in table 7 on page 20 . the offset values are 8-bit signed integer numbers for positive and negative offset-correction. 5.2.10. pfc, dmce and adc software controlled reset signals address 26 holds the reset flags for the dmce core, the pfc controller, and the adc interface. the reset flags are active if set to one and initially reset to zero. setting these flags can be used to when units are unused. 5.2.11. operational amplifier power down signals addresses 27 and 28 hold the power-down flags for all analog signal operational amplifiers. bits 0 to 7 of address 27 control the voltage follower for adc7 to adc0. bits 0 to 6 of address 28 control the enable state of the vdc voltage follower (bit 0), vac voltage follower (bit 1), dmce0 current amplifier (bit 2), , pfc current amplifier (bit 4), adc buffer amplifier (bit 5), and reference voltage buffer amplifier (bit 6). the msb (bit 7) of address 28 can be used to power-down the bias supply for all amplifiers. disabling of the operational amplifiers is performed by setting individual flags to one, initially all flags are set to zero. note that disabling the current amplifier of dmce0 will in turn disable the three associated phase voltage read-back comparators. 5.2.12. spi unit low-pass filter settings low-pass filtering is available for both the AMG-XB404 's system spi unit and the mcu-controlled spi unit. address 29 holds the time constants for each spi unit's input signal low pass filter. the value stated for spilp specifies the filter depth of the low pass filter for the system spi as a multiple of system clock cylces. the value stated for spilp2 specifies the filter depth of the low pass filter for the mcu's spi unit. the time base of the filter is the system clock. a value of 0 for spilp deactivated low-pass filtering, this is the default value. 5.2.13. assignment of power outputs and high voltage read-back pins in order to accommodate any phase order with a minimum of wiring effort AMG-XB404 's gate driver outputs and high voltage feedback signals are connected to freely programmable physical ic pins. they are assigned using addresses 30 through 35. address 30 contains the configuration for the three pins associated with the u-phase of dmce0. bits 0 to 2 configure the high-side drive signal pin. when set to a value of 1 through 6 uh will be assigned to one of pin m0o1 through m0o6. when set to a value of 0 the pin m0o1 is driven to a static low state, when set to 7 the pin m0o1 will be driven to a static high state. bits 3 to 5 configure the low-side drive signal pin. when set to a value of 1 through 6 ul will be assigned to one of pin m0o1 through m0o6. when set to a value of 0 the pin m0o2 is driven to a static low state, when set to 7 the pin m0o2 will be driven to a static high state. bits 6 and 7 configure the output state read-back pin ru. when set to a value of 1 through 3 ru will be assigned to one of pin m0r1 through m0r3. when set to a value of 0 no read-back pin will be assigned. AMG-XB404 revision: a 2. nov. 2012 ? all rights reserved page 11 of 73
AMG-XB404 fully integrated single motor controller for electrical motors addresses 31 and 32 contain the configuration for the three pins associated with the v-phase, and w-phase of dmce0 respectively, assigned in analogous fashion to address 30. they control the assignment of vh, vl, wh and wl to m0o1 through m0o6, the static logic state of pins m0o3, m0o4, m0o5, and m0o6, and the position of the output state read-back pins rv and rw to m0r1 through m0r3. 5.2.14. dmce and pfc driver signal read-back addresses 36 and 37 are used to read back the logic level at the driver outputs of both dmce and the pfc, this can be used for system health checking. the msb of both addresses switches between analog and digital read back inputs. if m0rmux is set to 1, analog comparators are used for reading back dmce0 driver outputs, otherwise digital inputs are used. the same applies for m1rmux concerning dmce1 output read back. the analog and digital inputs rely in the same i/o-pads, so switching between those does not affect pin layout configuration. 5.2.15. band gap reference tuning setting address 38 holds the four bits wide band gap reference tuning setting, vbgtun, allowing for the on-chip reference voltage generator to be adjusted in steps of 0.4% per lsb. the initial setting of vbgtun is eight, corresponding to a native reference voltage. tuning of the reference will ensure the correct setting of all derived regulated voltages. 5.2.16. ofi direct read-back address 39 is used for reading the state of the m0ofi input pin , bypassing the configured polarity and low-pass filtering settings. 5.2.17. eeprom direct access address 40 gives access to the serial interface of the eeprom. bit 0 is used for serially writing data to and reading data from the eeprom. the serial clock signal is transmitted via bit 1. 5.2.18. mcu-accessible engineering mode enable bit 0 of address 41 holds the mcu-accessible engineering mode enable flag eme2. by setting eme2 to 1 the mcu can access the eeprom via address 40 of the io expander. to leave the self-programming mode eme2 is set to 0, this is the default value. this bit cannot be set by the spi bus master. 5.2.19. adc tun mode, dmce value offset selection bit 0 of address 42 holds the adc tuning mode flag, tunmode. when set the adc will perform a tune cycle with each conversion. by default tunmode is not set. bit 1 and bit 2 of address 42 must remain 0, this is the default value. bit 3 of address 42 holds the offset select flag, offssel, used to select the offset value of dmce0 when set to 1 , this is the default. for details see section 5.3 p. 16 . 5.2.20. adc sample triggers for test, supply voltage, and temperature address 43 gives access to additional adc request flags. bit 0, ireq, is used to trigger sampling of the dc bus voltage, rectified ac voltage, dmce 's current values and the pfc controller's current value. readiness is indicated by reading this flag as 0. bit 1, vddreq, is used to trigger sampling of 5v supply voltage. readiness is indicated by reading vddreq as 0. AMG-XB404 revision: a 2. nov. 2012 ? all rights reserved page 12 of 73
AMG-XB404 fully integrated single motor controller for electrical motors bit 2, treq, is used to trigger sampling of on-chip temperature values. readiness is indicated by reading treq as 0. 5.2.21. io expander overview bit 7 6 5 4 3 2 1 0 register name index address comment write/read addr[7:0] ioexpa - address register initial value 0 0 0 0 0 0 0 0 write - - - - - - - - ioexpd 0 ic revision read 0 0 0 0 0 0 1 1 write/read - - clk-lock clkoff reserved locked (read) eme tme 1 engineering and test mode enable lock indicator initial value - - 0 0 0 1 0 0 write ofires1 ofipol1 ofires0 ofipol0 reserved reserved dmce0pol dmce0oe 2 dmce output configuration read ofierr1 ofipol1 ofierr0 ofipol0 reserved reserved dmce0pol dmce0oe initial value 0 0 0 0 0 0 0 0 write/read swcpre[7:0] 3 switching controller pre- scaler low/high initial value 0 0 0 0 0 0 0 0 write/read - swcpre[14:8] 4 initial value - 0 0 0 0 0 0 0 write/read - - - - - - - pfcpol 5 pfc pwm output polarity initial value - - - - - - - 0 write/read reserved reserved cnt0x2 dmce0c1 6 dmce c1 values; pwm double frequency initial value 0 0 0 0 0 0 0 0 write/read dmce0c2[7:0] 7 dmce0 c2 value initial value 0 0 0 0 0 0 0 0 write/read reserved 8 reserved initial value 0 0 0 0 0 0 0 0 write/read flldiv[7:0] 9 fll down-scaler; low byte initial value 0 0 0 0 0 0 0 0 write/read - - - flldiv[12:8] 10 fll down-scaler; high byte initial value - - - 0 1 0 0 0 write mprec[3:0] - - - - 12 maximum precision; current fll precision read mprec[3:0] prec[3:0] initial value 1 0 1 0 - - - - write reserved - reserved dtc0ovr - dtc0rng[1:0] 13 output comparator read-back and dtc setup read reserved reserved reserved reserved dtc0ovr rw0 rv0 ru0 initial value 0 0 0 0 0 0 0 0 write/read adcoff[7:0] 14..25 adc offset registers initial value 0 0 0 0 0 0 0 0 write/ read - - - - adcres pfcres dmce0res reserved reserved d mce0res 26 unit reset flags initial value - - - - 0 0 0 0 table 2 a: io port expander registers AMG-XB404 revision: a 2. nov. 2012 ? all rights reserved page 13 of 73
AMG-XB404 fully integrated single motor controller for electrical motors bit 7 6 5 4 3 2 1 0 register name index address comment write/read adc[0:7] opampen ioexpd 27 operational amplifier and bias enable flags initial value 0 0 0 0 0 0 0 0 write/read biasen vref buffer e. adc buffer e. pfc current e. reserved dmce0 e. vac e. vdc e. 28 initial value 0 0 0 0 0 0 0 0 write/read spilp2[3:0] spilp[3:0] 29 spi low pass filter values initial value 0 0 0 0 0 0 0 0 write/read m0ruconf[1:0] m0ulconf[2:0] m0uhconf[2:0] 30 dmce0 u-phase configuration initial value 0 0 0 0 0 0 0 0 write/read m0rvconf[1:0] m0vlconf[2:0] m0vhconf[2:0] 31 dmce0 v-phase configuration initial value 0 0 0 0 0 0 0 0 write/read m0rwconf[1:0] m0wlconf[2:0] m0whconf[2:0] 32 dmce0 w-phase configuration initial value 0 0 0 0 0 0 0 0 write/read reserved reserved reserved 33 reserved initial value 0 0 0 0 0 0 0 0 write/read reserved reserved reserved 34 reserved initial value 0 0 0 0 0 0 0 0 write/read reserved reserved reserved 35 reserved initial value 0 0 0 0 0 0 0 0 write m0rmux - - - - - - - 36 dmce0 and pfc driver output read-back read m0rmux pi m0i[5:0] initial value 0 - - - - - - - write reserved - - - - - - - 37 reserved read reserved - reserved initial value 0 - - - - - - - write/read - - - - vbgtun[3:0] 38 band gap reference adjust initial value - - - - 1 0 0 0 write - - - - - - - - 39 mxofi direct read-back read - - - - - - reserved m0ofi initial value - - - - - - - - write - - - - - - ee_sclo ee_sdao 40 eeprom access port read - - - - - - - ee_sdai initial value - - - - - - 0 0 write/read - - - - - - - eme2 41 engineering mode enable - mcu only initial value - - - - - - - 0 write/read - - - - offssel - - tun- mode 42 adc tune mode selection; dmce offset selection initial value - - - - 0 0 0 0 write/read - - - - - treq vddreq ireq 43 additional adc functions port initial value - - - - - 0 0 0 table 2 b: io port expander registers 5.2.22. interrupt controller the AMG-XB404 supports ten interrupt sources. interrupts are enabled by setting the global AMG-XB404 revision: a 2. nov. 2012 ? all rights reserved page 14 of 73
AMG-XB404 fully integrated single motor controller for electrical motors interrupt enable flag gie and the desired per-interrupt interrupt enable flags to 1. if more than one interrupt signal is active the interrupt with the lowest interrupt vector will be executed first. the gie flag is disabled during interrupt vector execution and re-enabled when returning from an interrupt. it is possible to manually re-enable the gie flag during interrupt execution, and thus employ nested interrupts. as shown in table 3 all interrupts are indicated by interrupt flags in registers intconl and intconh. the interrupt enable flags twiie (two wire interface), txcie (uart transmission complete), rxcie (uart reception complete), and spiie (mcu spi ready) are contained in intconh. all other interrupt enable flags are contained in the control registers of the individual units as summarized in table 4 . bit 7 6 5 4 3 2 1 0 register name comment write - - - - - - - - intconl interrupt controller register; low byte read if_adc if_txc if_rxc if_twi extint if_tmr2 if_tmr1 if_tmr0 initial value 0 0 0 0 0 0 0 0 write - - - pfcie spiie rxcie txcie twiie intconh interrupt controller register; high byte read if_pfc if_spi 1 pfcie spiie rxcie txcie twiie initial value 0 0 1 0 0 0 0 0 table 3 : interrupt controller registers interrupt priority source auto clear interrupt events interrupt enable flag interrupt flag 1 tmr0 yes timer match input capture tcr8[7] intconl[0] 2 tmr1 yes timer match input capture tcr8[7] intconl[1] 3 tmr2 yes timer match input capture tcr16[7] intconl[2] 4 gpio no external interrupt portie intconl[3], portifr 5 uart rxc no data reception complete intconh[2] intconl[5] 6 uart txc no data transmission complete intconh[1] intconl[6] 7 twi no data reception/ transmission complete intconh[0] intconl[4] 8 adc no sampling finished adcconf[6] intconl[7] 9 spi no data transmission complete intconh[3] intconh[6] 10 pfc no dmce/pfc exception intconh[4] intconh[7] table 4 : interrupt sources AMG-XB404 revision: a 2. nov. 2012 ? all rights reserved page 15 of 73
AMG-XB404 fully integrated single motor controller for electrical motors 5.2.23. status register the status register sreg contains the global interrupt enable flag gie and the mcus status bits. these bits are the transfer flag (to), the half carry flag (ho), the signed flag (so), the twos complement overflow flag (vo), the negative flag (no), the zero flag (zo), and the carry flag (co) as summarized in table 5 . bit 7 6 5 4 3 2 1 0 register name comment write gie to ho so vo no zo co sreg mcu status register read gie to ho so vo no zo co initial value 0 0 0 0 0 0 0 0 table 5 : status register 5.3. analog data aquisition unit (adaq) the analog data aquisition block features the measurement of external voltages and their use for system control purposes. its heart is a single 10 bit 2m samples/s successive approximation register (sar) - adc. the adc is shared by the AMG-XB404 s dmce , pfc controller, and mcu. in addition it contains measuring amplifiers, a multiplexer and an adc interface. 5.3.1. adc interface the adc interface serves to arbitrate between all units requiring sample values and the adc. there are three general purpose adc channels, a voltage monitor channel and a temperature monitor channel dedicated to the mcu. conversion status and the results of these channels can be acquired by reading the adc's io registers via the on-chip bus. for the general purpose adc channel s conversions are triggered by port writes, the unit can raise an interrupt flag to indicate a completed conversion. the conversion status and result can be acquired by reading the adc interface's io registers . an analog multiplexer is used to select the desired internal or external signal source as shown in figure 8 . every adc channel has got a systematic offset. offset correction values are stored in the adcoff registers in the io port expander module (see section 5.2 p. 9 ). adc channel s , pfc vac, pfc vdc, chip-temperature and vdd are automatically corrected by their offset values when sampled. AMG-XB404 revision: a 2. nov. 2012 ? all rights reserved page 16 of 73
AMG-XB404 fully integrated single motor controller for electrical motors 5.3.2. analog input signal ranges the input signal range at the analog input pins of the general purpose adc channel s , the dc bus voltage, the rectified ac voltage, dmce 's current signal s and pfc ac current signal is a nominal input voltage range of 0..5v. the adc input voltage for the current signal inputs can be calculated as: v o = ? v i ? r 2 r 1 v offs and is shown in figure 9 (see also figure 8 p. 17 ). v offs of the dmce 's current channel s and the pfc's current channel is different because the dmce 's current s may have either polarity whereas the pfc's current is always smaller than zero. . AMG-XB404 revision: a 2. nov. 2012 ? all rights reserved page 17 of 73 figure 8 : xb404 adaq block schematic dmce eoc tun 8 bit on-chip bus 9 vdd monitor dmce0 current pfc ac voltage pfc dc voltage v offs temperature monitor muxsel pfc adc bus-if trig rdy soc 10 data adc measuring amplifier adc ch. 0..2 + - v cc + - + - + - pfc ac current r 2 r 1 trig rdy d a t a i 10 v d c l p 12 v a c l p 14 1/x v d c r l p 23 v d c l p 15 mux 1 1 2 5 v o v i
AMG-XB404 fully integrated single motor controller for electrical motors . for the dc current channel v offs is set to nominally 445 mv. for the ac current channel v offs is set to about 24 mv. for improved noise rejection and accuracy the rectified ac voltage and the dc bus voltage values are digitally low-pass filtered using iir filters, the low-pass filtered values vaclp and vdclp are fed directly to the pfc controller. vdclp is fed to the dmce core and an inverter. the low-pass filtered signal value for vaclp and vdclp can be calculated as follows: vaclp n = 15 16 ? vaclp n ? 1 vac n vdclp n = 31 32 ? vdclp n ? 1 vdc n 5.3.3. triggering analog signal acquisition sampling of the general purpose adc channels 0 through 7 is triggered by writing the connected flag within the register adcreq as one. completion is indicated by reading the connected flag in register adcint as one. the rectified ac voltage and the dc bus voltage are sampled at the analog inputs vac and vdc. sampling of these signals is triggered automatically every 1024 cycles of the system clock if dmce core is not reset. sampling can also be triggered by setting the indirect request flag, ireq, via the io expander (see section 5.2.20. , page 12 ). the raw sample value can be read via the adc's registers (see table 6 , p. 19 ), the low-pass filtered value using the respective dmce and pfc registers. sampling of dmce current offset values is triggered when a zero-vector is set by the dmce's pwm unit. it is performed autonomously at the beginning of each pwm cycle when all low-side switches of the pwm module are in on-state, if the dmce is not reset. sampling can also be triggered by setting the indirect request flag, ireq, via the io expander (see section 5.2.20. , page 12 ). the raw sample value can be read using the adc unit's registers as shown in table 7 , p. 20 , the low-pass filtered value using the dmce's register. an on-chip temperature sensor provides a 0..1.8v analog signal that is sufficient for measurements with an accuracy of 1.25 k/bit. the calibration setting of the temperature sensor is stored in the eeprom. temperature sampling is triggered by setting the treq flag within the io expander, see section 5.2 p. 9 . the treq flag will be reset to 0 when a temperature sample has been acquired. AMG-XB404 revision: a 2. nov. 2012 ? all rights reserved page 18 of 73 figure 9 : adc current input characteristic v offs (iac) pfc current range i in v offs (idc) n adc 1023 +i 0 dmce current range -i
AMG-XB404 fully integrated single motor controller for electrical motors a voltage divider with an accuracy of 8 mv/bit is used to monitor the voltage at the a5v pin. voltage sampling is triggered by setting the vddreq flag within the io expander, see section 5.2 p. 9 . the vddreq flag will be reset to 0 when a a5v sample has been acquired. the supply voltage can be calculated as: a5v = adc vmon ? 5 ? 1.8v 1023 5.3.4. accessing adc sample data, adc interrupts the adc is configured through the adcconf register shown in table 6 p. 19 . the adc channel to be addressed is chosen by setting the four least significant bits of the adcconf register (as shown in detail in table 7 , p. 20 ). by setting adcie to 1 adc interrupt generation is enabled. the interrupt flags for adc channel 0 to 7 can be accessed through the interrupt flag register adcint. to reset a specific interrupt flag the corresponding bit in the interrupt reset register adcires must be written as 1. the two least significant bits of the conversion result are accessed through bits four and five of adcconf. the eight most significant bits are held by the data register adcd. the most significant bit's value must always be retrieved first. the adc can be run in either synchronous or asynchronous mode. by setting the msb in adcconf to 0 synchronous mode is activated. in synchronous mode adc channel 0 through 7 will only be sampled after an acquisition of the dc bus voltage to reduce distortions caused by the ipm. in synchronous mode the sampling rate is limited to the dmce's pwm frequency. in asynchronous mode sampling of adc channel 0 through 7 will be performed at the next available time, i.e. when no adc channel with a higher priority is pending. any adc acquisition initiated by either dmce or the pfc controller has a higher priority than adc channel 0 through 7. only temperature measurements, d5v measurements and tuning cycles have a lower priority. the pending adc channel with the lowest number will always be sampled first (see also table 7 ). bit 7 6 5 4 3 2 1 0 register name comment write async adcie sel[1:0] 0 0 adcch[1:0] adcconf adc configuration register read async adcie adcd[1:0] 0 0 adcch[1:0] initial value 0 0 0 0 0 0 0 0 write 0 0 0 0 0 0 irch[1:0] adcires adc interrupt reset register; channel 0..2 initial value 0 0 0 0 0 0 0 0 read adcd[9:2] adcd adc data register initial value 0 0 0 0 0 0 0 0 write 0 0 0 0 0 0 reqch[1:0] adcreq adc request register; channel 0..2 initial value 0 0 0 0 0 0 0 0 read 0 0 0 0 0 0 intadcch[1:0] adcint adc interrupt flag register; channel 0..2 initial value 0 0 0 0 0 0 0 0 table 6 : xb404 adc registers AMG-XB404 revision: a 2. nov. 2012 ? all rights reserved page 19 of 73
AMG-XB404 fully integrated single motor controller for electrical motors code priority adc channel offset register address (io expander module) adcch[3] adcch[2] adcch[1] adcch[0] input pin triggered by 0 6 14 0 0 0 0 adc channel 0 adc request register 1 7 15 0 0 0 1 adc channel 1 2 8 16 0 0 1 0 adc channel 2 8 14 22 1 0 0 0 vdc hardware timer 9 15 23 1 0 0 1 vac 10 2 - 1 0 1 0 m0idc dmce0 12 1 - 1 1 0 0 pfci pfc 13 16 24 1 1 1 0 on-chip temperature sensor io expander flags 14 17 25 1 1 0 1 d5v 15 4 - 1 1 1 1 m0idc dmce0 table 7 : xb404 adc channel encoding in adcconf[3:0] delay tuning is the process of adjusting internal signals of the adc to compensate for temperature and process-dependent delays. tuning is performed once after ic reset and must be repeated in the face of large temperature changes. upon reset tuning mode is off, tuning mode can be enabled by setting the tunmode flag within the io expander, see section 5.2 p. 9 . AMG-XB404 revision: a 2. nov. 2012 ? all rights reserved page 20 of 73
AMG-XB404 fully integrated single motor controller for electrical motors 5.4. digital motor control engine (dmce) the AMG-XB404 dmce 's features: ? 32 bit motor control processing unit (mcpu) with single precision floating point format running at 64 mhz ? 384 words x 24 bits program memory ? 128 floating point (32 bit) registers ? register-mapped hardware ports to control pwm unit from mcpu ? 2 lookup-tables (32 floating point entries each) ? pwm unit including phase current reconstruction and dead time compensation ? safety shut-down on external error event (e.g. over-current) AMG-XB404 revision: a 2. nov. 2012 ? all rights reserved page 21 of 73 figure 10 : dmce block schematic m0o1 m0o2 m0o3 m0o5 m0o6 m0o4 m0r1 m0r2 m0r3 bus if m0ifo mcpu program memory dmce 0 pwm vac vdc . . . m0i m0ifb int 8 bit on-chip bus register file 32 data 7 addr 24 data 9 addr 32 data 7 24 data 9 addr addr 23 12 12 12 vdcr noi iv vdc rdy iu 15 fpudat taqu_wr ioffs_wr nw_wr td_wr nu_wr nv_wr fpuen int adc if adc measuring amplifier mux adaq
AMG-XB404 fully integrated single motor controller for electrical motors 5.4.1. motor control processing unit (mcpu) the dmce contains a single precision floating point motor control processing unit (mcpu) capable of executing computationally expensive motor control algorithms. the harvard architecture mcpu executes programs stored in a 384 words deep program memory sram. the mcpu can execute eight different operations. they are performed on the mcpu's 128 directly addressed registers, 64 indirectly addressed registers, and register-mapped hardware ports. each register represents a 32 bit single precision floating point number. the eight supported commands have a uniform width of 24 bits and the format is shown in figure 11 . the following table gives an overview of each command's function. op operation description 0 r c = r a r b add r a and r b and store result in r c . 1 r c = r a - r b subtract r b from r a and store result in r c . 2 r c = r a ? r b multiply r a with r b and store result in r c . 3 r c = sin r a - 2 calculate sine of (r a -2) and store result in r c . r a must satisfy 0 r a (/2+0.1). 4 r c = cos r a ' - 2 get the corresponding cosine value for the last sine calculation and store the result in r c . for angles greater that (/2) the command returns cos(r a -2)+4. consequently, 4 needs to be subtracted from the result in these cases. 5 jump a t perform an unconditional jump to the address given in a t . 6 jump a t if r a 0 perform a jump to the address given in a t if r a is negative. 7 r c = r a calculate square root of r a and store result in r c . table 8 : mcpu commands floating point values used by the AMG-XB404 are similar to the ieee754 standard. figure 12 shows the bit assignments. s denotes the number's sign. 0 stands for a positive sign and 1 for a negative sign. the number's exponent e is offset by +127 i.e. exponents ranging from -127 to 128 can be processed. the mantissa m is normalized and always includes a hidden 1. the mantissa's value becomes 1. m in binary format. a floating point number's value can thus be calculated as s ? - 1 : 1 ? 1. m ? 2 e ? 127 . for the sake of simplicity, the mcpu can represent neither 0 nor infinity and has no means of reporting AMG-XB404 revision: a 2. nov. 2012 ? all rights reserved page 22 of 73 figure 11 : mcpu command format 0 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 op r a r b r c a t 21 22 23 figure 12 : floating point number format 0 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 s e m 31 30 29 28 27 26 25 24 23 22 21
AMG-XB404 fully integrated single motor controller for electrical motors exceptions. consequently, any algorithm implemented on the AMG-XB404 must avoid or handle these limitations in order to prevent malfunction. 5.4.2. register file out of the 128 directly addressed registers, registers 0 through 9 are special purpose registers reserved for the communication with the pwm unit (see table 9 p. 23 ). registers can be read from and written to by the dmce and via the 8 bit on-chip bus. two times 32 indirectly addressed registers can be read from and written to via registers 8 and 9. the address index is set via register 6. for the details of indirect addressing see table 9 . address register name read value register name write value 0 rdy ready flag, sign bit set at the start of each pwm cycle nu u-phase pwm value in bits [14:0] of mantissa 1 iu u-phase current produced by virtual current sensor, value in bits [14:0] of the mantissa, offset by 8192 nv v-phase pwm value in bits [14:0] of mantissa 2 iv v-phase current produced by virtual current sensor, value in bits [14:0] of the mantissa, offset by 8192 nw w-phase pwm value in bits [14:0] of mantissa 3 vdc dc bus voltage, value in bits [11:0] of the mantissa td pwm dead time td measured in mcpu clock cycles, value in bits [8:0] of mantissa 4 vdcr 1 divided by dc bus voltage, value contained in bits [22:0] of the mantissa taqu minimum current sample acquisition time taqu measured in mcpu clock cycles, value in bits [14:0] of mantissa 5 ioffs zero current offset contained in bits [13:0] of mantissa ioffs zero current offset, value in bits [13:0] of mantissa 6 noi no current obtained if sign bit of this register is set index index for indirect addressing, value in bits [22:18] of mantissa 7 mcpue n mcpu enable flag, bit 0 of the mantissa mcpue n mcpu enable flag, if bit 0 of mantissa is set to zero mcpu will be reset 8 irega read from indirect addressed registers a irega write to indirect addressed registers a 9 iregb read from indirect addressed registers b iregb write to indirect addressed registers b table 9 : special purpose registers 5.4.3. pwm unit the pwm unit is responsible for generating the pwm timings for each of the three phases according to the duty cycles requested by the mcpu. voltage vectors are chosen by the pwm unit to enable a safe reconstruction of the motor's phase currents. duty cycles are specified by the values of nu, nv, and nw written to register addresses 0 to 2 (see table 9 ). for a duty cycle dc between 0 and 1 the floating point value for nu is calculated as: nu = 2 dc ? 2 ? 22 . the same equation applies to nv and nw. moreover, the pwm unit performs autonomous dead-time compensation by means of the internally assigned feedback pins ru0/1, rv0/1, rw0/1 ensuring the equality of intended and factual duty cycle for each phase. the pwm unit is also in charge of triggering voltage and current sampling at the appropriate time slots within each pwm cycle and reconstructing the u and v phases currents (iu, iv). the 12 bit wide values of iu and iv are available to the mcpu core through the special purpose registers at addresses 1 and 2 (see table 9 ). the special purpose register at address 3 contains the dc bus voltage floating point value vdc, which is calculated as: vdc = 2 vdc adc ? 2 ? 22 . with vdc adc being the dc bus voltage integer value from the adc. the inverted dc bus voltage's floating point value vdcr can be accessed at address 4 and is calculated as: vdcr = 2 1 vdc adc ? 2 ? 22 . AMG-XB404 revision: a 2. nov. 2012 ? all rights reserved page 23 of 73
AMG-XB404 fully integrated single motor controller for electrical motors the pwm unit is capable of indicating a faulty current reconstruction by means of the noi flag in register 6. the 18 least significant bits form the no-current error vector noiv. the most significant seven bits of them indicate an error in calculation of the duty cycle. the three least significant bits indicate an error in dead-time compensation. the noi flag is set if any bit of noiv is set. the pwm unit requires the offset value of the current channel operation amplifier for current reconstruction. this floating point value called ioffs has to be written to address 5 of the register file and is calculated as: ioffs = 2 o ? 2 ? 22 . with o being the adcs integer value with zero current. in order to prevent an inverter shoot-through the pwm unit inserts an adjustable delay between the high-side and low-side active states. the delay value is set via register 3 and is a 9 bit wide multiple of the mcpus clock cycle. the floating point value of this dead-time register is calculated as: td = 2 t delay ? f fpu ? 2 ? 22 . a minimum sample acquisition time is guaranteed by setting the value of register 4, taqu. the acquisition time is a 15 bit wide multiple of the mcpus clock cycle. the floating point value of the acquisition time register taqu is calculated as: taqu = 2 t aqu ? f fpu ? 2 ? 22 . 5.4.4. accessing the dmce via the on-chip bus bit 7 6 5 4 3 2 1 0 register name comment write/read d0[7:0] m0dat0 data register d0 bits [7..0] initial value 0 0 0 0 0 0 0 0 write/read d1[7:0] m0dat1 data register d1 bits [15..8] initial value 0 0 0 0 0 0 0 0 write/read d2[7:0] m0dat2 data register d2 bits [23..16] initial value 0 0 0 0 0 0 0 0 write/read d3[7:0] m0dat3 data register d3 bits [31..24] initial value 0 0 0 0 0 0 0 0 write adr[7:0] m0adr address register initial value 0 0 0 0 0 0 0 0 write - - - - adr[8] op[2:0] m0sc status and command register read - - - - - - - start initial value - - - - - - - 0 write - - - - - - - 0 dmcesel dmce select register read - - - - - - - dmcesel initial value - - - - - - - 0 table 10 : dmce access registers the dmce has six dedicated 8 bit registers on the 8 bit on-chip bus, see table 10 . the dmce can only be accessed via the spi interface if the ic is not locked, see section 5.7.1 page 37 . the dmcesel flag in the lsb of the dmce select port determines which dmce is accessed. if set to zero dmce0, i.e. mcpu0, is accessed . four data ports are used to write and read program or register data. the 7 bit wide register address is set using the address register. the 9 bit wide program memory address is set using the address register for the eight least significant bits and bit three of the command register for the most significant bit. read and write operations are triggered by writing the status and command ports three least significant bits. all available commands are summarized in table 11 . AMG-XB404 revision: a 2. nov. 2012 ? all rights reserved page 24 of 73
AMG-XB404 fully integrated single motor controller for electrical motors when the dmce is disabled the on-chip bus has read and write access to the program memory for debugging purposes. code description 0 no valid command, zero indicates finished command on register reads 1 load command rom value to data registers d0, d1, d2 2 load data registers d0, d1, d2 to dmce command rom 3 load data registers d0, d1, d2, d3 to dmce data register 4 load register value to data registers d0, d1, d2, d3 5 load pwm cycle counter 1 to data registers d0, d1, d2, d3 6 load program counter to data register d0, d1 7 load mcpu idle indicator to lsb of data register d0 table 11 : dmce command register codes normally, program memory and register file information are stored in the eeprom and loaded into the respective memory by the mcu. the idle indicator is used when monitoring register and is reset by the ready flag. while the idle flag is 1, register values remain stable (see figure 13 ). therefore, it is guaranteed that only register values of a single pwm cycle are read at a time. 1 number of pwm cycles since reset AMG-XB404 revision: a 2. nov. 2012 ? all rights reserved page 25 of 73 figure 13 : idle indicator idle reg rdy register value remains stable pwm cycle n+1 register value may change pwm cycle n
AMG-XB404 fully integrated single motor controller for electrical motors 5.4.5. power stage over-current protection in the event of over-current a dedicated hardware unit for the dmce will turn off all logic outputs, indicate this error via a dedicated io expander flag (see section 5.2.16. , p. 12 ), and optionally trigger the shared dmce/pfc interrupt of the mcu. if the power stage connected to the AMG-XB404 provides a digital over-current fault indicator (ofi) input, the ofi input acts as a digital input with a logic threshold level of 0.5v nominally. if no digital over-current fault indicator flag is available, the ofi input acts as an analog comparator with a trip level of 0.5v nominally, which is the standard power stage module trip level. in this case the shunt resistor connected to the power stage needs to be dimensioned accordingly. the AMG-XB404 can handle power stage modules having any combination of driver and over- current feedback polarity, see figure 14 above. as described in section 5.2 , p. 9 five dedicated signals control the polarity of drivers and over-current fault input, error indication and reset, and enabling of the driver outputs. the over-current fault input signal ofi is low-pass filtered digitally, it needs to continually indicate an error for at least 1s nominally to detect an over-current condition. the pin order of the driver and high voltage feed-back pins can be configured freely as described in section 5.2.13. , p. 11 . AMG-XB404 revision: a 2. nov. 2012 ? all rights reserved page 26 of 73 figure 14 : over-current protection block schematic pwm mo6 cnt xor r ifoerr dmce f mcu xor ofi mo1 ifores . . . pol vhi uhi ifop whi uli vli wli & en + - 0.5v trip level xor
AMG-XB404 fully integrated single motor controller for electrical motors 5.5. power factor correction controller (pfc) the AMG-XB404 pfc's features: ? fully configurable digitally controlled pfc ? constant frequency, continuous conduction mode (ccm) ? 16 bit risc core ? 256 words x 22 bits program memory ? 64 words x 16 bits data memory ? adjustable pwm-frequency, range: 5khz ~ 150khz, spread spectrum option ? on-chip over-current and short-circuit protection, brown-out control ? on-chip ac-phase-locked sinusoidal oscillator (45hz ~ 65hz) for improved ac line noise reduction the AMG-XB404 's pfc controller supports standard boost-topology power factor correction depicted in figure 15 . it is designed to achieve iec61000-3-2 level pfc performance when combined with appropriately dimensioned power electronics and line filtering. the pfc controller interacts directly with the adc unit to acquire the rectified ac voltage, the dc bus voltage, and the rectified ac current value. it generates a pulse width modulated logic-level switching signal connected to an external gate driver circuit. a detailed block schematic of the pfc controller is shown in figure 16 p. 28 . the pfc controller is built around an autonomous 16 bit risc processor core supporting 15 different instructions (see table 12 p. 29 ). it runs at the same high clock frequency as the dmce . a 22 bits wide, 256 words deep sram serves as the processor's program memory. all instructions operate on a 6 bit data address space which is divided into address ranges for general purpose registers, constants, hardware ports, and values stored in a dedicated sram (see table 13 p. 31 ). AMG-XB404 revision: a 2. nov. 2012 ? all rights reserved page 27 of 73 figure 15 : simplified pfc controller application schematic ac r2 r1 r7 r6 r5 r3 r4 hvdc v aux vac vdc pfcifb pfci agnd l1 d1 c1 rect. pfc contr. adc 8 bit on-chip bus pfc_pwm drv measuring amplifier hv
AMG-XB404 fully integrated single motor controller for electrical motors the unit includes a pwm generator that can be used to generate frequencies in a range of 5~150khz. a hardware-based pseudo random number generator can be used to generate a spread-spectrum pwm signal. the pfc controller is able to set an interrupt line to indicate errors to the mcu. a hardware-based counter with an adjustable increment can be used to form a phase- locked signal that is synchronous to the mains frequency. AMG-XB404 revision: a 2. nov. 2012 ? all rights reserved page 28 of 73 figure 16 : pfc controller block schematic pfc_pwm bus if 16 bit risc core pfc controller lut . . . int 8 bit on-chip bus 16 data 6 addr 22 data 8 addr 16 data 22 data 8 addr pwm program memory register file data memory cnt 32x16 bit memory constants 6 addr 11 rr lfsr hw ports vac pfci pfcifb adc if adc vdc mux measuring amplifier 12 delay 11 randmax 13 endl 13 endh 10 dcnt 10 rc 15 corang 16 angle adaq
AMG-XB404 fully integrated single motor controller for electrical motors 5.5.1. pfc instruction set description the 15 supported commands have a uniform width of 22 bits and the format shown in figure 17 . a, b, c being register or memory locations upon which the operation op is executed. operations can also use the immediate values i1, i2, and i3 which are part of the command word. table 12 p. 29 gives an overview of each commands function. op mnemonic operation clock cycles description 0 jmp jump i1 1 jump to 8 bit address immediate i1 1 brn jump i1 if a 0 1 (2) jump to 8 bit address immediate i1 if register/memory a is negative 2 brp jump i1 if a 0 1 (2) jump to 8 bit address immediate i1 if register/memory a is positive 3 brz jump i1 if a = 0 1 (2) jump to 8 bit address immediate i1 if register/memory a is zero 4 st c = a 1 (2) store register/memory a in register/memory c 5 add c = a b 1 (2) add register/memory a and register b and store result in register/memory c 6 sub c = a ? b 1 (2) subtract register b from register/memory a and store result in register/memory c 7 div angle = cord _ i : cord _ q 50 divide cord_i by cord_q in cnt (1-15) iterations, result stored in angle; for iterations register cnt is used, begin with setting angle to zero 8 cord cord _ i = 23167 ? sin angle 2 14 ? 2 cord _ q = 23167 ? cos angle 2 14 ? 2 80 execute cordic algorithm on cord_i , cord_q , etc. in cnt 1-15 iterations, result stored in cord_i , cord_q; for iterations register cnt is used 9 mul m = a ? b 1 (2) multiply two registers a , b or a memory a and a register b and store result in internal register m 10 shmr c = m ? i3 1 shift multiplier result in internal register m right by i3 bits and store result in target memory/register c 11 shl c = a ? i3 1 (2) shift register/memory a left by i3 bits and store result in register/memory c 12 shr c = a ? i3 1 (2) shift register/memory a right by i3 bits and store result in register/memory c 13 sti c = i2 1 store immediate i2 (max. 12 bit) in register/memory c 14 sync wait while pfc _ iac == 0 1 wait for pfc_iac impulse table 12 : pfc instruction set (the clock cycle values in braces denote the number of clock cycles if an sram value needs to be read during command execution.) AMG-XB404 revision: a 2. nov. 2012 ? all rights reserved page 29 of 73 figure 17 : pfc command format 0 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 op a b c i2 21 i3 i1
AMG-XB404 fully integrated single motor controller for electrical motors 5.5.2. pfc data memory description the structure of the data memory is shown in table 13 . the first seven addresses of the pfc controller's data memory hold general purpose registers which can be used in any combination to execute commands in a minimum number of clock cycles. note that register values are modified by sine value computation and division. consequently, their value must be rescued to data memory as required. address 8 through 15 provide access to eight constant read-only values. addresses 16 through 29 are used for hardware ports which are described hereafter. addr type name or value number of valid bits 1 registers tmp 16 2 cord_i 16 3 cord_q 16 4 angle 16 5 anglesum 16 6 cnt 16 7 testreg 16 8 constants 0 1 9 1 1 10 512 10 11 8176 13 12 9948 14 13 700 10 14 430 9 15 4095 12 16 hardware ports vac 14 17 vdc 15 18 iac 10 19 corang 15 20 rr 11 21 randmax 11 22 pfc_iac 1 23 delay 12 24 pfc_en 1 25 rc 10 26 interrupt 1 AMG-XB404 revision: a 2. nov. 2012 ? all rights reserved page 30 of 73
AMG-XB404 fully integrated single motor controller for electrical motors addr type name or value number of valid bits 27 dcnt 10 28 endl 13 29 endh 13 32..63 sram sram0 ... sram31 16 table 13 : data memory overview (constants and hardware ports are used as registers) the pfc controller uses center-aligned pwm signals as shown in figure 18 . the start and end of a pwm cycle are determined by the pwm reference counter's maximum value which equals the value of the endh register divided by two. the pwm period has thus a multiple of endh / f fpu . endh is double buffered, i.e. its value can be set at any time by writing the value to the buffer endh but will only be applied to the internally used register endhi in the next pwm cycle. consequently, randomized duty cycles can be set asynchronously. the duty cycle of the pwm is determined by the ratio of endhi and endli, i.e. dc = endli / endhi . endl is double buffered as well and will be updated to its internally used register endli at the same time as endh to endhi (see figure 18 ). due to the low-pass filtered characteristic of the current signal its sampling must be delayed relative to the pwm signal. setting the value of the delay register will postpone current sampling by an adjustable number of pfc clock cycles. each sampling of the rectified ac current is followed by a sampling of the rectified ac voltage. the dc bus voltage value is updated whenever a new sample delivered to the dmce core . the pfc has no means of triggering dc voltage value sampling. normally, calculation and sample acquisition are synchronized by the means of the pfc controller's sync operation which halts execution until the lsb of the pfc_iac register becomes 1, indicating the completion of rectified ac current sampling. the pfc_iac register can also be read directly. AMG-XB404 revision: a 2. nov. 2012 ? all rights reserved page 31 of 73
AMG-XB404 fully integrated single motor controller for electrical motors ad-converted, rectified ac voltage, dc voltage, and rectified ac current are buffered in and can be read from the registers vac, vdc and iac. as shown in figure 18 the rectified ac current is sampled in the middle of the pfc transistor's on-period which coincides with the zero-crossing of the pfc's reference counter. the pfcs pwm output pfc_pwm can be inverted by setting the pfcpol bit in the io port expander (see table 2 p. 14 ). the pfc controller's pseudo random number generator makes use of an lfsr 2 capable of producing values with a length between four and eleven bits. a new random value will be generated each time rr is read. the random values' length is set through the randmax register, its most significant set bit determines the length of the generated value. with n denoting the position of the most significant set bit, a pseudo random value between one and 2 n 1 ? 1 is calculated. if randmax is smaller than 16 a four bit value will be generated. an optimum feedback seed is chosen automatically for any bit width. the value returned by rr may be greater than randmax because only the most significant set bit is taken into account by the pfc algorithm. the pfc algorithm may re-read rr if a value greater than randmax is encountered. the read/write register rc returns a 10 bit wide reference counter value which is incremented once every dcnt clock cycle s . dcnt has a width of ten bits and can be adjusted to obtain a variable frequency ramp signal on rc. rc can usually be employed to generate a clean reference sine value for power factor correction. the pfc controller can signal an interrupt to the mcu by setting the lsb of the interrupt hardware port to 1. upon interrupt execution the interrupt flag must be cleared by either the pfc's algorithm or the mcu by setting the lsb of the interrupt register to 0. the pfc_en hardware port is reserved for enabling and disabling power factor correction. the 2 linear feedback shift register AMG-XB404 revision: a 2. nov. 2012 ? all rights reserved page 32 of 73 figure 18 : pfc's pwm cycle endli endli n+1 endhi endl delay cnt adc conversion pfc_pwm adc_start cnt measurement endhi endh pfc_iac load values load values n measurement load values
AMG-XB404 fully integrated single motor controller for electrical motors pfc algorithm is in pll mode when the lsb of pfc_en is set to 0. in this state the reference counter is synchronized with the mains frequency, the pwm output is not modulated. power factor correction is started by setting the lsb of pfc_en to 1. the pwm output will be modulated accordingly. the value of the corang register returns a lookup-value of an incremental angle used when performing a cordic algorithm for sine and cosine calculation. the value is addressed by the four least significant bits of the cnt register. this register is meant for the cordic hardware's internal use only. addresses 32 to 63 of the data memory are used to access a 16 bit wide 32 words deep data sram. in contrast to data registers, reading constants and ports from the sram requires two clock cycles. moreover, a data sram address may not be used in arbitrary combination with other values. see table 12 p. 29 for a list of all valid commands. 5.5.3. accessing the pfc controller via the on-chip bus the pfc controller can only be accessed via the spi interface if the ic is not locked, see section 5.7.1 page 37 . as shown in table 14 two 8 bit registers, one data register, and one command and status register can be used to communicate with the pwm. when writing data to the pfc controller it is written to the data register before executing the write by sending the appropriate command to the command and status register. data is read from the pfc controller by sending the appropriate read command to the command and status register and reading back one byte of the data register. values wider than eight bits are transferred using multiple 8 bit transfers. bit 7 6 5 4 3 2 1 0 register name comment write/read dat[7:0] pfcd data register initial value 0 0 0 0 0 0 0 0 write cmd[7:0] pfcsc status and command register read itcnt[6:0] start initial value 0 0 0 0 0 0 0 0 table 14 : pfc controller registers AMG-XB404 revision: a 2. nov. 2012 ? all rights reserved page 33 of 73
AMG-XB404 fully integrated single motor controller for electrical motors command description 0x11 set address register 0x22 set buffer register [7:0] to value in data register 0x33 set buffer register [15:8] to value in data register 0x44 set buffer register [21:16] to value in data register 0x55 set data register to value in buffer register [7:0] 0x66 set data register to value in buffer register [15:8] 0x77 set data register to value in buffer register [21:16] 0x88 set buffer register [15:0] to pfc data ram or register 0x99 set data from pfc data ram or port to buffer register [15:0] 0xaa set buffer register [21:0] to pfc program ram 0xbb set data from pfc program ram to buffer register [21:0] 0xcc enable pfc controller 0xdd disable pfc controller 0xee set data register to value of the pfc program counter table 15 : pfc bus interface command codes AMG-XB404 revision: a 2. nov. 2012 ? all rights reserved page 34 of 73
AMG-XB404 fully integrated single motor controller for electrical motors 5.6. switch mode power supply (smps) the AMG-XB404 smps's features: ? constant frequency, discontinuous conduction mode (dcm) ? primary coil current control input ? one directly regulated output voltage ? other output voltages (depending on the transformer) indirectly regulated ? independent low frequency start-up clock source ? automatic clock selector to enable system clock after start-up ? clock-scaling for higher pwm-frequencies (10khz ~ 150khz) ? energy saving cycle-skipping mode for low levels of output power ? on-chip over-current protection with disable function the AMG-XB404 's switch mode power supply operates in constant frequency, discontinuous conduction mode (dcm). depending on the external circuitry it is capable of generating at least one variable output voltage. one of these voltages is directly controlled, the others indirectly. as an example in figure 19 an adjustable output voltage v aux of 15v is generated and controlled by using an external voltage divider (see r5 and r6 in figure 19 ). the output voltage v aux of the switching supply is regulated in such a way that the reference voltage level at the swvi pin is equal to an internal reference. the swvfb pin is used for the compensation of the sense amplifier. the primary coil's current control loop is closed by means of the swi input pin. the logic level signal swdrv drives a simple external level shifting circuit consisting of t2 through t4, and r9 which in turn drives the power transistor t1 attached to the primary winding of the switching supply's transformer. the level shifter supply of nominally 15v is fed by the same AMG-XB404 revision: a 2. nov. 2012 ? all rights reserved page 35 of 73 figure 19 : example switch mode power supply application schematic (simplified) hv smps swi swvref swvfb swdrv r1 d1 d2 c1 c6 d3 t4 r8 r2 c3 d5 d4 r6 r5 c4 vref v aux (15v) r3 swv swvdd c2 r7 c5 r4 t1 t3 dgnd t2 d6 c7 d5v reg 5v r9
AMG-XB404 fully integrated single motor controller for electrical motors transformer winding as the output voltage v aux . the constant switching frequency of the smps can be determined by a low-precision rc oscillator which is part of the smps, or by an adjustable, digitally generated reference clock signal which is adjustable via the io expander (see section 5.2 p. 9 ). at start-up when no digitally generated clock is available, the rc oscillator is used. typically, the rc oscillator's frequency is significantly lower than the optimum switching frequency to accommodate the oscillator's lack of precision. this means that less than the rated power can be drawn at start-up. to achieve full performance the smps must be operated using the well-defined, digitally generated switching frequency. the smps is supplied through the swvdd pin and must be biased for start-up. zener diodes are used to provide the supply voltage for the level shifter and smps. the smps's internal reference voltage at the swvref pin needs to be stabilized using a capacitor connected to dgnd. the smps shares the digital ground pin dgnd with the rest of the ic. as shown in figure 19 a secondary winding of the transformer can be used to derive a secondary, indirectly regulated output voltage, helping to improve over-all efficiency. in the presence of low loads the smps enters a cycle skipping mode. the smps is designed to limit the maximum power via the duty cycle of the switching signal. the shunt resistor r4 must be dimensioned in such a way that the transformer's specifications are not exceeded for the given switching frequency, the highest possible voltage across r4 (approx. 1.26v), and the given regulated output voltage. if this maximum load is exceeded for a duration of more than one second (typical) the smps's output will be disabled in order to protect the circuit. the secondary switching output is short-circuit protected by monitoring the power-on reset signal. if the voltage present at the digital 5v pin of the AMG-XB404 remains below the minimum operating voltage for longer than one second the smps's output will be disabled in order to protect the circuit. the AMG-XB404 requires a power-on cycling to resume to normal operation after the occurrence of one of the error conditions described above. AMG-XB404 revision: a 2. nov. 2012 ? all rights reserved page 36 of 73
AMG-XB404 fully integrated single motor controller for electrical motors 5.7. micro controller unit (mcu) the AMG-XB404 's mcu features: ? 8 bit avr compatible risc core ? 1kbyte data sram ? 16384 words x 16 bit program memory ? 8 mhz system clock ? watch dog timer ? three general purpose interrupt-generating timers ? three channel adc function ? 17 general purpose ios see section 5.11 page 60 for a summary of the mcu's instruction set. 5.7.1. programming and debug interface the programming interface is used to access the mcu's 16 bits wide and 16384 words deep program memory. programs are executed from shadow sram whose contents are loaded from an eeprom after power-on reset. for testing purposes the loading process can be stopped, and re- started, by using commands 19 and 20 (see table 17 , p. 38 ). the mcu executes the program starting at address 0 of the sram. the unit is also used to debug the mcu core. the programming and debug interface is accessible via the system spi interface only, the associated bus addresses are undefined for the mcu core. before any functionality of the programming and debug interface is available the ic must be unlocked. this is accomplished by setting the sram address to zero and sending the first 1024 words stored in program memory, which serve as a key, to the AMG-XB404 . unlocking is achieved by setting low byte and high byte to the data registers and issuing the unlock command for each data word (see table 17 on page 38 ). the address will be incremented automatically. the lock/unlock status can be checked through the io expander as described in section 5.2.2 , p. 9 . table 16 gives a summary of the registers associated with the programming and debug interface. an overview of the available commands is shown in table 17 . AMG-XB404 revision: a 2. nov. 2012 ? all rights reserved page 37 of 73
AMG-XB404 fully integrated single motor controller for electrical motors bit 7 6 5 4 3 2 1 0 register name comment write d0[7:0] srd0 data register, lower byte read d0[7:0] initial value 0 0 0 0 0 0 0 0 write d1[7:0] srd1 data register, higher byte read d1[7:0] initial value 0 0 0 0 0 0 0 0 write a0[7:0] sra0 address register, lower byte read pcr[7:0] initial value 0 0 0 0 0 0 0 0 write a1[7:0] sra1 address register, higher byte read mcu_clk en ee_done 0 pcr[12:8] initial value 0 0 0 0 0 0 0 0 write 0 0 0 cmd[4:0] srsc status and command register read 0 0 0 0 0 ee_rdy ee_found status bit initial value 0 0 0 0 0 0 0 0 table 16 : program and debug interface registers code description purpose 0 write 16 bit data {d1,d0} to shadow sram at address {a1,a0} shadow sram programming 1 load shadow sram data to {d1,d0} 2 enable mcu reset mcu reset 3 disable mcu reset 4 load low byte of mcu stack pointer to d0 mcu debugging 5 load mcu status register to d0 6 load mcu general purpose register to d0 7 load mcu ram to d0 8 set break point a[1:0] to {d1,d0} 9 erase break point a[1:0] 10 continue after break point and disable stepping 11 enable stepping 12 load high byte of mcu stack pointer to d1 13 load program counter value to {a1,a0} 16 check data in {d1, d0} against contents of eeprom ic unlock 17 start sram march c- test sram test 19 start loading eeprom to shadow sram eeprom loading 20 stop loading eeprom to shadow sram table 17 : command register codes for program and debug interface 5.7.1.1. program memory initialization after power-on reset the ic probes for an eeprom by sending a device address word and evaluating its acknowledge status. if an eeprom is detected, its contents will be copied to shadow sram and the mcu's reset signal will be released. AMG-XB404 revision: a 2. nov. 2012 ? all rights reserved page 38 of 73
AMG-XB404 fully integrated single motor controller for electrical motors if no eeprom is found reset will not be released, and a no detect status will be indicated via the unit's status and command register. 5.7.1.2. shadow sram reads and writes for quick mcu program development the ic's shadow sram can be read and written. before reading and writing the mcu needs to be reset using command 2 detailed in table 17 . in order to execute writes to shadow sram memory the 16 bits of data of the program word are written to the two 8 bit data registers, srd0 and srd1. next, the 14 bit wide address is written to sra0 and sra1[5:0]. the actual write is initiated by writing command 0 to the status and command register srsc. in order to execute a read from shadow sram memory, the 14 bit address is written to sra0 and sra1[5:0]. by writing command 1 to srsc the sram read is executed and the 16 bits of data can be read from srd0 and srd1 via the 8 bit on-chip bus after srsc[0] has been read as 0. 5.7.1.3. eeprom rads and writes to permanently store program and configuration data the eeprom is used. each byte inside the eeprom corresponds to one half of a shadow sram program word. eeprom address 0 contains the low-byte of shadow sram address 0, eeprom address 1 contains the high-byte of shadow sram address 0, eeprom address 2 contains the low-byte of shadow sram address 1, etc. serial two-wire communication is performed via port 40 of the io expander (see table 2 b, p. 14 ), and is activated by enabling engineering mode via port 1 of the io expander. figure 20 shows the start and stop conditions state changes of the serial data line sda when the serial clock scl is high indicate either the start condition (falling edge of sda) or the stop condition (rising edge of clk). consequently, sda may only change its state when scl is low during data transfers, master (io expander) and slave (eeprom) must sample sda when scl is high (see figure 20 ). every start condition is followed by an address cycle as shown in figure 21 . the 7 bit wide address is transmitted with its msb first and is followed by the read/write flag. data is transmitted from io expander to eeprom if this flag is set to 0 and from slave to master if set to 1. the eeprom acknowledges an address cycle by pulling sda to low during the clock cycle following the read/write flag. in slave mode the two wire communication interface will only acknowledge the address cycle if the sent address and the address mask are valid. an address cycle can be followed by a data cycle or a stop condition. AMG-XB404 revision: a 2. nov. 2012 ? all rights reserved page 39 of 73 figure 20 : two-wire communication start stop conditions scl change sda sda sample sda stop start
AMG-XB404 fully integrated single motor controller for electrical motors as shown in figure 22 a data cycle contains eight data bits and one acknowledge bit. data is sent msb first. the receiving side acknowledges the received data by pulling sda low. when data is sent from io expander to eeprom the eeprom may set stopreg to send a non- acknowledge after receiving the next byte from the io expander, thus indicating that it will receive no more data. the eeprom will enter a passive state after stopreg has been set until a start condition is received. if data requested by the io expander is not ready to be sent by the eeprom the eeprom will pull the serial clock to low until the data is ready. this is the only case in which the eeprom influences the serial clock. all serial communication is initiated by a device address word (see figure 23 ) indicating the eeprom address and the read/write access mode, writes have the lsb set to 0, reads have the lsb set to 1. for the AMG-XB404 the eeprom address is always zero. the device address word will be acknowledged if the ic is ready. eeprom writes the 256 kbit eeprom is capable of up to 64-byte page writes. a page write operation requires the device address word followed by a 16 bits wide start byte address, up to 64 bytes of data, and a stop condition to initiate a self-timed eeprom write. this is shown in figure 24 . it can be seen that all data and address bytes need to be acknowledged by setting the data line low. writes start at the given byte address, the address is incremented automatically. AMG-XB404 revision: a 2. nov. 2012 ? all rights reserved page 40 of 73 figure 21 : serial two-wire communication address cycle scl from io expander sda from eeprom sda from io expander resulting sda ack lsb r/w address[6:0] msb figure 22 : serial two-wire communication data cycle scl from io expander sda from receiver sda from transmitter resulting sda ack lsb 8-bit data msb figure 23 : device address word 1 a2 a1 a0 r/w 1 0 0 msb lsb
AMG-XB404 fully integrated single motor controller for electrical motors after initiating a page write the eeprom will not acknowledge requests for typically 5ms. consequently, waiting for the end of the write operation consists of sending a start condition followed by a device address word, and evaluating the acknowledge non-acknowledge status. the next write or read command may be sent after receiving an acknowledge signal from the eeprom. eeprom reads as shown in figure 25 eeprom reads consist of a dummy write operation, consisting of a write device address word followed by a 16 bits wide start byte address, followed by a second start condition and a read device address word. following this command sequence the eeprom will return bytes starting at the specified address, and increment the read address for every received acknowledge. the maximum byte address is 32767, after that the address will roll over to address 0. the sequential read operation is terminated by sending a stop condition. the serial bus' timing is shown in figure 26 below, while the timing values can be found in chapter 8.3. , p. 68 . AMG-XB404 revision: a 2. nov. 2012 ? all rights reserved page 41 of 73 figure 24 : write procedure * s t a r t m s b sda line l s b r / w a c k w r i t e note: * don't care bits. first word address n device address second word address n a c k a c k data n data (n+x) a c k a c k s t o p m s b l s b figure 25 : read procedure * s t a r t m s b sda line l s b r / w a c k w r i t e note: * don't care bits. first word address n device address second word address n a c k a c k s t a r t device address r e a d a c k data n data (n+x) a c k n o a c k s t o p dummy write
AMG-XB404 fully integrated single motor controller for electrical motors 5.7.1.4. march c- sram test a structural sram test is started by using command 17. during memory test data register srd0 is read back as 1. when the test is finished srd0 indicates the test result, 0 for pass, and 2 for fail. 5.7.1.5. eeprom calibration and user data space located at the bottom of the eeprom there is a file system storing calibration data regarding the adc, rc oscillator and others, along with dmce and pfc firmware. calibration data include the fll divider, as well as the adc offset and gain values. after power-on reset the eeprom's content is copied to the shadow sram, this includes the calibration and user data space. AMG-XB404 revision: a 2. nov. 2012 ? all rights reserved page 42 of 73 figure 26 : eeprom serial bus timing figure 27 : calibration and user data space mcu program 2b bf 2c 2d ff ... ... ... 6b eeprom 0 32k
AMG-XB404 fully integrated single motor controller for electrical motors the data space is organized in records (an example is shown in figure 27 ). every record consists of a 1 byte id number and a data item, which depending on the id number has a certain length. records are read id first and then data. figure 28 shows the record format. once an id is reserved it cannot be deleted. there are four categories of id's to differentiate data field lengths, see table 18 . id number data length 0x01..0x3f 1 byte 0x40..0x7f 2 byte 0x80..0xbf 4 byte 0xc0..0xfe n byte table 18 : types of id's id numbers 0x01 to 0x1f and 0xc8 to 0xdf can be used for specific, application related data, such as constants and parameters for example. id numbers 0x00, 0xe0 to 0xfe are reserved. id number 0xff is used to indicate the end of the data space. reading the data space starts at the highest possible address of the shadow sram and continues until id number 0xff is found. an id overview is shown in table 19 . id number comment 0x00 reserved 0x01..0x1f available for custom data 0x2b band gap reference adjustment value 0x2c..0x35 reserved 0x36..0x3f adc offset with buffering channels: vdc, vac, 7..0 0x40..0x5f available for custom data 0x65 adc vdd calibration value 0x66 adc temperature calibration value 0x67 fll calibration parameter 2 0x68 fll calibration parameter 1 0x69 fll calibration parameter 0 0x6a fll temperature calibration value 0x6b fll divider 0x6c..0x75 adc gain without buffering channels: vdc, vac, 7..0 0x76..0x7f adc gain with buffering channels: vdc, vac, 7..0 AMG-XB404 revision: a 2. nov. 2012 ? all rights reserved page 43 of 73 figure 28 : record format address + length + 1 [byte] address + 0 [bytes] data id
AMG-XB404 fully integrated single motor controller for electrical motors id number comment 0x80..0x9f available for custom data 0xbf time stamp (seconds since epoch) 0xc0 dmce0 program 0xc1 dmce0 registers 0xc2 reserved 0xc3 reserved 0xc4 pfc program 0xc5 pfc registers 0xc6 powerstage0 pin order 0xc7 reserved 0xc8..0xdf available for custom data 0xe0..0xfe reserved 0xff end of data space table 19 : id overview 5.7.1.6. debug interface the debug interface allows read access to the mcu's status register, stack pointer, program counter, general purpose registers, and ram (see commands 4, 5, 6, 7, 12, 13 in table 17 ). for accessing general purpose registers a 5 bit address {sra0[4:0]}, and for ram data a 10 bit address {sra1[1:0],sra0} has to be specified. four break points can be set and enabled using command 8. when the program counter reaches a break point the mcus clock is stopped. this is indicated by mcu_clken going low (see table 16 ). the continue command 10 is used to re-enable the mcus clock. a stepping mode is also available. in this mode the mcu clock will be stopped after each command. the stepping mode is enabled using command 11. the mcu clock is re-enabled by using the continue command. 5.7.2. general purpose input output interface (gpio) the gpio block interfaces the ics general purpose io pins, grouped in 8 bit wide io ports. the AMG-XB404 features 17 general purpose ios(see figure 29 ). the gpio block relays io pins to uart , twi and spi as shown in table 20 . io pin signal direction condition comment portb[0] uart tx o uarten uart data output enabled if uarten=1, else uart disabled portb[1] uart rx i uart data input enabled if uarten=1, else uart disabled portb[2] twi scl io twien twi clock pin enabled if twien=1, else twi disabled portb[3] twi sda io twi data output enabled if twien=1, else twi disabled portb[4] tmr 0 oc o oc0 ^ portbo[4] timer 0 output compare portb[5] tmr 1 oc o oc1 ^ portbo[5] timer 1 output compare portb[6] tmr 2 oc o oc2 ^ portbo[6] timer 2 output compare portc[2] tmr 2 ic i timer 2 input capture, always connected portc[4] spi scs io spien spi chip select pin enabled if spien=1, else spi disabled portc[5] spi sdo o spi data output pin enabled if spien=1, else spi disabled portc[6] spi sdi i spi data input pin enabled if spien=1, else spi disabled portc[7] spi sclk io spi clock pin enabled if spien=1, else spi disabled table 20 : xb404 dedicated function gpio ports AMG-XB404 revision: a 2. nov. 2012 ? all rights reserved page 44 of 73
AMG-XB404 fully integrated single motor controller for electrical motors portb[0] and portb[1] become tx and rx line of the uart if uarten is set. the polarity of the tx line can be inverted by setting portbo[0] to 1 for non-inverted operation it needs to be set to 0. the polarity of the rx line is set via portbo[1] in the same way. see section 5.7.3 p. 47 for a detailed description of the uart. portb[2] and portb[3] become the two wire interface's scl and sda pins when the twi is enabled. see section 5.7.5 p. 49 for a detailed description of the twi. portb[6:4] are used for the three timers' output compare signals. portb[5] is connected to 8 bit timer0, portb[5] is connected to 8 bit timer1 and portb[6] is connected to 16 bit timer2. the value of the output compare flag is xor-ed with the value in portbo[6:4] respectively, thus allowing to invert the signal as required. portc[7:4] are used for the spi controller's sclk, scs, sdi, and sdo pins. the polarity of the clock can be inverted by setting portco[4] to 1, the standard non-inverting behaviour is achieved by setting portco[4] to 0. see section 5.7.4 p. 48 for a detailed description of the spi. portc[2] is connected to timer2. if portco[2] is set to 0 rising signal edges are detected by the timer, if set to 1 falling signal edges are detected. see section 5.7.6 p. 52 for a detailed description of all timers. porte[2:0] is shared with the general purpose adc channel s see section 5.3 page 16 for details. note that dedicated gpio functions may override output pins so these pins are not controlled by the output buffer register. when reading a port, the actual input is read instead of the buffer content, even if the port is configured to be an output. this needs to be considered when doing bit- manipulation on gpio ports with special functions enabled. for example portbo[0] determines tx polarity when uarten is set. when reading back the port, portb[0] keeps the actual tx line instead of the tx polarity setting. so these bits must always be written as intended, not as read. AMG-XB404 revision: a 2. nov. 2012 ? all rights reserved page 45 of 73
AMG-XB404 fully integrated single motor controller for electrical motors AMG-XB404 revision: a 2. nov. 2012 ? all rights reserved page 46 of 73 figure 29 : xb404 gpio overview csr data addr twi gpio block tcr ocr cnt 8/16 bit timers ctrl data spi ucsr rxb txb uart on-chip bus spien twien scli scso scsi scse sclko sclki sclke sdi csen sdo tx uarten rx ic sclo oc sdai sdao p o r t b [ 7 : 0 ] out_en out in out_en out in . . . p o r t c [ 7 : 2 ] out_en out in out_en out in . . . p o r t e [ 2 : 0 ] out_en out in out_en out in . . .
AMG-XB404 fully integrated single motor controller for electrical motors bit 7 6 5 4 3 2 1 0 port comment write portbo[7] oc2 oc1 oc0 portbo[3:2] uartrxpol uarttxpol b port b data register initial value 0 0 0 0 0 0 0 0 read portbi[7:0] write portco[7:5] scklipol portco[3] ic2pol ic1pol ic0pol c port c data register initial value 0 0 0 0 0 0 0 0 read portci[7:2] write portbe[7:0] b port b output enable register initial value 0 0 0 0 0 0 0 0 read portbe[7:0] write portce[7:2] c port c output enable register initial value 0 0 0 0 0 0 0 0 read portce[7:2] write portie[7:0] - interrupt enable register initial value 0 0 0 0 0 0 0 0 read portie[7:0] write portifr[7:0] - interrupt flag register initial value 0 0 0 0 0 0 0 0 read portifr[7:0] write porteo[2:0] e port e data register initial value 0 0 0 0 0 0 0 0 read portei[2:0] write portee[2:0] port e output enable register initial value 0 0 0 0 0 0 0 0 read portee[2:0] table 21 : xb404 gpio registers 5.7.3. universal asynchronous receiver transmitter interface (uart) the uart's io pins are mapped to gpio pins if enabled (see figure 29 ). the baud rate is adjustable. all data is sent and received in blocks of a start bit, eight data bits, and a stop bit (see figure 30 ). data is sent by writing a byte to the transmit buffer register txb, the most recent received byte can be read from the receive buffer rxb, see table 32 p. 58 . the uart is configured by writing to the control and status register ucsr. as shown in table 23 the interface is enabled by setting uart_en to 1, the baud rate is adjusted by setting the lower three bits as shown in table 22 . if the ready flag rdy is set to 1 the interface has sent all pending data and is ready for another transmission. if the stop bit of an incoming transmission is not correct a framing error is indicated by the framing error flag ferr being set to 1. an overflow error will be indicated by the flag oerr. it is set to 1 if a byte is received before the previous byte has been read from rxb. the rx and tx polarities can be set by writing uartrxpol respectively uarttxpol (see AMG-XB404 revision: a 2. nov. 2012 ? all rights reserved page 47 of 73 figure 30 : uart data transfer 6 5 7 0 stop bit start bit 4 3 2 1
AMG-XB404 fully integrated single motor controller for electrical motors table 21 p. 47 ). if uartrxpol is set to 1, the rx line is interpreted active low, otherwise it's interpreted active high. if uarttxpol is set to 1, data is sent out active low, otherwise it's sent out active high. active high is the default setting for both lines. the uart has got two interrupt signals that can be enabled as shown in section 5.2.22 p. 14 . an rx interrupt is generated when a new byte is received and stored in rxb, the interrupt flag is reset by reading the rx buffer. a tx interrupt is generated when the byte in txb has been sent, the interrupt flag is reset by writing to the tx buffer. code baudrate[2:0] baud rate 0 000 9600 1 001 19200 2 010 38400 3 011 57600 4 100 115200 table 22 : uart baud rates bit 7 6 5 4 3 2 1 0 register name comment write uart_en - - - - baudrate[2:0] ucsr status and control register read uart_en rdy ferr oerr 0 baudrate[2:0] initial value 0 0 0 0 0 0 0 0 write rxb[7:0] rxb receive buffer read rxb[7:0] initial value 0 0 0 0 0 0 0 0 write txb[7:0] txb transmit buffer read txb[7:0] initial value 0 0 0 0 0 0 0 0 table 23 : uart registers 5.7.4. serial parallel interface (spi) the spis io pins are mapped to gpio pins (see figure 29 p. 46 ). the spi can be run as a master or a slave. in master mode the mcu can communicate with one or more spi slaves. in slave mode an spi master can control the spi. there is a control and a data register which are shown in detail in table 24 . spi chip select scs and spi clock sclk are always driven by the master. they frame and time the transmission. data is transferred in blocks of up to eight bits, data is always sent out synchronously via sdo and received via sdi using a single 8 bit shift register controlled by the serial clock. figures 31 and 32 show an 8 bit spi transmission. by default sdo and sdi are sampled on the rising edge of sclk, sampling will take place on the falling edge of sclk if the clock's polarity is inverted in the gpio register (see section 5.7.2 p. 44 ). AMG-XB404 revision: a 2. nov. 2012 ? all rights reserved page 48 of 73 figure 31 : spi timing scs sdo sdi sclk 6/1 5/2 4/3 3/4 2/5 1/6 0/7 7/0 7/0 6/1 5/2 4/3 3/4 2/5 1/6 0/7
AMG-XB404 fully integrated single motor controller for electrical motors bit 7 6 5 4 3 2 1 0 register name comment write data[7:0] spidat data register read data[7:0] initial value 0 0 0 0 0 0 0 0 write - mode[1:0] spien msblsb csen - - spictrl control register read - mode[1:0] spien msblsb csen wcol trf initial value 0 0 0 0 0 0 - - table 24 : spi registers to enable the spi the flag spien has to be set to 1. with the msblsb flag set to 1 the msb will be transferred first, otherwise the lsb is transferred first. the flag csen controls the usage of the chip select line, if set to 1 chip select is used, otherwise chip select will be ignored. wcol and trf are read-only flags for write collision wcol and readiness for next transmission trf. in master mode a collision occurs if new data is written to spidat while the previous transmission has not been finished. the spis mode controls master/slave operation and the serial clock speed in master mode. it is selected by setting mode[1:0] as shown in table 25 . mode ctrl[6] ctrl[5] clock speed master 0 0 2 mhz master 0 1 500 khz master 1 0 125 khz slave 1 1 - table 25 : spi mode selection the spi has got a single interrupt flag which can be enabled through the interrupt control register (see section 5.2.22 p. 15 ). the interrupt is raised after each completed transmission. the interrupt flag is cleared by reading from or writing to spidat. 5.7.5. two wire interface (twi) the gpios portb[2] and portb[3] become the two wire interface's serial clock scl and serial data sda pins when the twi is enabled by setting twena in config_reg to 1 (see table 26 ). a pull-up resistor is required at each pin. the two wire interface can be configured to operate in master or slave mode by setting mode in config_reg, master mode is enabled by setting the flag to 1. the twi master can initiate writes to and reads from a twi slave. AMG-XB404 revision: a 2. nov. 2012 ? all rights reserved page 49 of 73 figure 32 : spi communication principle scsi sdi sdo sclki 6 5 4 3 2 1 0 7 1 2 3 4 5 6 7 0 scso sdo sdi spi master 6 5 4 3 2 1 0 7 1 2 3 4 5 6 7 0 spi slave rxb sclko txb txb rxb
AMG-XB404 fully integrated single motor controller for electrical motors the twi address register and twi address mask register share the same mcu bus address. the msb determines which register is set if written to. reading the register returns the twi address register, the address mask register cannot be read. if the address set by the master (addr) masked by twiam and the address set in the slave twia masked by twiam match, the address is considered valid. this can be expressed as addr twiam = twia twiam , denotes a bit-wise and. with a twiam set to binary 1111100 addresses 124, 125, 126 and 127 can be addressed. bit 7 6 5 4 3 2 1 0 register name comment write twena - mode rw startreg stopreg prescaler[1:0] twisc configuration register; write-only initial value 0 - 1 0 0 0 0 0 read flag rstart rstop rw startreg stopreg datawf datarf status register; read-only initial value 0 0 0 0 0 0 0 0 write 1 addrm[6:0] twiadr address mask register write 0 addr[6:0] address register read 0 addr[6:0] initial value 0 0 0 0 0 0 0 0 write data[7:0] twidat data register read data[7:0] initial value 0 0 0 0 0 0 0 0 table 26 : twi registers state changes of the serial data line sda when the serial clock scl is high indicate either the start condition (falling edge of sda) or the stop condition (rising edge of clk). consequently, sda may only change its state when scl is low during data transfers, master and slave must sample sda when scl is high (see figure 33 ). every start condition is followed by an address cycle as shown in figure 34 . the 7 bit wide address is transmitted with its msb first and is followed by the read/write flag. data is transmitted from master to slave if this flag is set to 0 and from slave to master if set to 1. the slave acknowledges an address cycle by pulling sda to low during the clock cycle following the read/write flag. in slave mode the twi will only acknowledge the address cycle if the sent address and the twis address mask are valid. an address cycle can be followed by a data cycle or a stop condition. AMG-XB404 revision: a 2. nov. 2012 ? all rights reserved page 50 of 73 figure 33 : start stop conditions scl change sda sda sample sda stop start
AMG-XB404 fully integrated single motor controller for electrical motors as shown in figure 35 a data cycle contains eight data bits and one acknowledge bit. data is sent msb first. the receiving side acknowledges the received data by pulling sda low. when data is sent from master to slave the twi slave may set stopreg to send a non- acknowledge after receiving the next byte from the master, thus indicating that it will receive no more data. the slave will enter a passive state after stopreg has been set until a start condition is received. if data requested by the master is not ready to be sent by the slave the slave will pull the serial clock to low until the data is ready. this is the only case in which the slave influences the serial clock. setting rw in config_reg to 0 in master mode will send data from master to slave. if rw is set to 1 data will be received by the master. the transmission of the data held in data_reg is started by setting startreg to 1. the transmission will be stopped after sending any pending data by setting stopreg to 1. the 2 bit prescaler determines the serial clock speed in master mode (see table 27 ). prescaler[1:0] comment 0 400 khz serial clock 1 200 khz serial clock 2 100 khz serial clock 3 50 khz serial clock table 27 : serial clock settings the status register status_reg is used to monitor transmissions (see table 26 p. 50 ). the flag bit indicates a transmission error i.e. non-acknowledge. in slave mode rstart and rstop are set to 1 by the twi upon a received start respectively stop condition and will be reset automatically after the address cycle is done. datawf rises to 1 if data can be written to data_reg. datawf will be set to 0 if data is written to data_reg. datarf rises to 1 when received data can be read from data_reg. datarf will be set to 0 if data is read from data_reg. the twis interrupt is set when datawf or datarf are set. the interrupt flag remains set until data_reg is read from or written to. it may also be cleared by disabling the twi module via the config_regs twena bit. AMG-XB404 revision: a 2. nov. 2012 ? all rights reserved page 51 of 73 figure 35 : twi data cycle scl from master sda from receiver sda from transmitter resulting sda ack lsb 8-bit data msb figure 34 : twi address cycle scl from master sda from slave sda from master resulting sda ack lsb r/w address[6:0] msb
AMG-XB404 fully integrated single motor controller for electrical motors 5.7.6. general purpose timers the AMG-XB404 has got two 8 bit timers and one 16 bit timer. all timers are controlled by the mcu via the on-chip bus. each timer has got one dedicated interrupt generated by match and input capture timer events. timer interrupts can be enabled independently. interrupt flags are cleared automatically upon timer interrupt execution or ic reset. table 29 lists all timer-related registers. each timer can be configured to use an individual system clock pre-scaler ratio. timers have got an 8 or 16 bit wide counter register cnt, which can be read from and written to, and an output compare register ocr, containing the compare value for the timer match function, which also can be read from and written to. each timers control register contains the individual timers pre-scaler setting in its least significant 3 bits (see table 28 ). the timer will be disabled if the pre-scaler is set to 0. prescaler[2:0] timer reference clock 0 timer off 1 mcu clock frequency 2 mcu clock frequency divided by 2 3 mcu clock frequency divided by 4 4 mcu clock frequency divided by 16 5 mcu clock frequency divided by 64 6 mcu clock frequency divided by 256 7 mcu clock frequency divided by 512 table 28 : clock modes for 8 bit and 16 bit timers if the timer is enabled the timers counter register will be incremented according to the pre-scaler setting. if the counter overflows cnt changes from 65535 to 0 (16 bit timer) or 255 to 0 (8 bit timers). each timer has got two principle modes, match mode and input capture mode. match mode is always active. in addition input capture mode can be enabled if input capture enable icen is set to 1. in match mode (see figure 36 ) the interrupt flag is set if cnt equals ocr, and interrupt enable inten in tcr is set to 1. if reset on match rom in tcr is set to 1 cnt will be reset to 0. an interrupt on match is only generated if input capture enable icen is set to 0. by setting ocen and the according gpio portb output enable to 1 the output compare output oc is enabled (see table 21 p. 47 ). oc is set to 0 on reset and will be toggled on match if reset on match is enabled. by writing to tcr[4] oc can be pre-set. if reset on match is disabled oc is set to 0 on match and set to 1 on counter overflow. AMG-XB404 revision: a 2. nov. 2012 ? all rights reserved page 52 of 73 figure 36 : timer match mode (assuming immediate interrupt handling) oc int ocr cnt rom
AMG-XB404 fully integrated single motor controller for electrical motors in input capture mode (icen=1, see figure 37 ) an interrupt is generated if a rising edge at the input capture input pin ic is detected and interrupt enable inten in tcr is set to 1. cnt will be stopped and can be read via the bus. by writing 1 to tcr[6] cnt will continue to be incremented. bit 7 6 5 4 3 2 1 0 register name comment write tmrie icen ocen ocir resom prescaler[2:0] tcr8 8 bit timer control register read tmrie icen ocen ocir resom prescaler[2:0] initial value 0 0 0 0 0 0 0 0 write cnt[7:0] tcnt8 8 bit timer counter register read cnt[7:0] initial value 0 0 0 0 0 0 0 0 write ocr[7:0] ocr8 8 bit timer output compare register read ocr[7:0] initial value 0 0 0 0 0 0 0 0 write tmrie icen ocen ocir resom prescaler[2:0] tcr16 16 bit timer control register read tmrie icen ocen ocir resom prescaler[2:0] initial value 0 0 0 0 0 0 0 0 write tcntl[7:0] tcntl16 16 bit timer counter register; low byte read tcntl[7:0] initial value 0 0 0 0 0 0 0 0 write tcnth[15:8] tcnth16 16 bit timer counter register; high byte read tcnth[15:8] initial value 0 0 0 0 0 0 0 0 write ocrl[7:0] ocrl16 16 bit timer output compare register; lower byte read ocrl[7:0] initial value 0 0 0 0 0 0 0 0 write ocrh[15:8] ocrh16 16 bit timer output compare register; higher byte read ocrh[15:8] initial value 0 0 0 0 0 0 0 0 table 29 : general purpose timer registers, registers for second 8bit timer are identical to first and not shown 5.7.7. watchdog timer the dedicated watchdog timer can be used to restart program execution starting at the reset vector address (zero) if the mcu fails to update it periodically. the watchdog is controlled by the watchdog timer control register wdtcr, see table 30 . the watchdog is enabled by setting the watchdog enable flag wde to 1. the time-out value is set AMG-XB404 revision: a 2. nov. 2012 ? all rights reserved page 53 of 73 figure 37 : timer input capture mode (assuming immediate interrupt handling) ic set icen to 1 cnt int
AMG-XB404 fully integrated single motor controller for electrical motors using the watchdog pre-scaler wdp, the time-out value is calculated as: t to = 2 17 wdp f mcu . following a regular power-on reset the watchdog time-out flag wdto is set to 1. if the reset vector is executed following a watchdog time-out wdto will be set to 0, thus indicating a watchdog time- out event. bit 7 6 5 4 3 2 1 0 register name comment write - - - - wde wdp[2:0] wdtcr watchdog timer control register read - - - wdto wde wdp[2:0] initial value - - - 1 0 0 0 0 table 30 : watchdog timer control register AMG-XB404 revision: a 2. nov. 2012 ? all rights reserved page 54 of 73
AMG-XB404 fully integrated single motor controller for electrical motors 5.8. system clock the AMG-XB404 system clock's features: ? supports three different system clock modes ? nominal 64mhz system clock ? internally generated clock can be put out to feed external circuitry the clock mode is set by connecting the clksel and xo_ osel pin to d5v or dgnd as shown in table 31 : ? on-chip rc-ramp-based, frequency locked loop (fll) -controlled, vco-generated on- chip clock ? crystal or resonator oscillator-based, fll-controlled, vco-generated on-chip clock ? clock input from external clock input pin clksel xo_osel clkio description 0 0 input external clock input signal via clkio pin 0 1 output/off internal rc-ramp based clock generation 1 (crystal) output/off internal crystal/resonator based clock generation table 31 : clock source configuration the recommended clock source of the ic uses an integrated rc-ramp of nominally 60 s for adjusting the on-chip vco. as shown in figure fehler: referenz nicht gefunden this ramp signal serves as the time standard for the fll block which generates the system clock. the fll block uses a 13 bit wide divider ratio specifying the number of vco clock cycles per rc-ramp. the mcu clock frequency is generated by dividing the vco's clock frequency by eight, consequently all system clocks are in-phase signals. initially, the fll divider ratio is set to 2048, resulting in an approximately 48 mhz clock output for a typical rc-ramp at room temperature. the flls divider ratio is trimmed via the io port expander (see section 5.2 p. 9 ) to achieve the target clock frequency of 64mhz. a clock rate error of less than 2 % over the operating temperature range can be achieved by AMG-XB404 revision: a 2. nov. 2012 ? all rights reserved page 55 of 73 figure 38 : oscillator and fll block schematic rc- ramp pfc vco 8 mcu (8mhz) dmce adaq 64 mhz cxo fll + - clko clki xo_osel xo dec. clksel s1 s2 s2 8mhz cxoclk rcout rcres s1 256
AMG-XB404 fully integrated single motor controller for electrical motors providing a temperature-dependent fll divider ratio based on a polynomial function of chip temperature. the initial divider value and the temperature coefficient are measured and stored in the eeprom during final test. they can be used by the mcu to perform temperature compensation in combination with the adc value of the temperature channel. an external 8mhz crystal or resonator can be attached to the pins xo and xo_osel. the cxo clock signal generated by the inverter-based oscillator is divided by 256 to obtain a 32s time standard. in combination with the default divider ratio a system clock of 64mhz results and no adjustments to the divider ratio are required. the AMG-XB404 's system clock signal can also be input via the clkio pin when configured appropriately. in order to prevent external noise from interfering with the clock selection setting, the clklock flag can be set via the io expander. when set, the flag will preserve the selection preset at the time of setting clklock, see section 5.2. , page 9 for details. when an internal clock source is selected the clkio pin acts as a clock output, allowing for system clock monitoring. clkio output may be disabled by setting clkoff within the io expander, see section 5.2. , page 9 for details. 5.9. power-on and system reset the AMG-XB404 has got a dedicated active-low reset signal input pin named nresin. the reset input is low-pass filtered for improved noise rejection. any reset impulse shorter than 2s (typical) will be discarded. as shown in figure 39 system reset must be handled differently for externally and internally generated clock signals. for internally generated clocks the active-low fll lock signal at the output pin nresout must be connected to nresin. for externally generated clocks the active- low output pin npor of the power-on reset unit must be connected to nresin. an external reset circuit may also feed nresin directly but must ensure that the ic operating conditions are guaranteed as discussed below. the power-on reset unit monitors the supply voltage d5v and keeps the fll unit reset while the supply voltage is too low for supplying the AMG-XB404 . when d5v rises above the safe threshold voltage v por the ic's fll reset signal por will be released with power-on delay of t por . the fll will then start to adjust the AMG-XB404 's vco and indicated a frequency lock by setting its lock signal to low, the lock signal can be observed at pin nresout. the start-up to lock time of the fll is defined as t lock . AMG-XB404 revision: a 2. nov. 2012 ? all rights reserved page 56 of 73 figure 39 : AMG-XB404 reset scheme block schematic lp filter power-on reset nresin d5v npor system reset nresout short for internal clock short for external clock fll lock
AMG-XB404 fully integrated single motor controller for electrical motors if d5v drops below the brown-out voltage v bo the power-on reset unit will trigger a reset of the fll unit which will in turn reset the digital core of the AMG-XB404 . the AMG-XB404 will resume operation with the power-on reset cycle described above as soon as d5v rises above v por . power- on reset and brown-out reset scenarios are detailed in figure 40 . AMG-XB404 revision: a 2. nov. 2012 ? all rights reserved page 57 of 73 figure 40 : power-on reset and brown-out reset timing vdd resout/ lock brown-out v por v bo t lock vd v vd min t por v vdd typ t por t lock v vd typ v vd min undefined power-on reset npor undefined
AMG-XB404 fully integrated single motor controller for electrical motors 5.10. on-chip bus register summary table 32 : on-chip bus register summary AMG-XB404 revision: a 2. nov. 2012 ? all rights reserved page 58 of 73 indirect 10 bit address direct 6 bit address register name comments page 0x0 ~ 0x1f r0~r31 general purpose registers 0x21 0x1 m0dat0 m0 data register 0 0x22 0x2 m0dat1 m0 data register 1 0x23 0x3 m0dat2 m0 data register 2 0x24 0x4 m0dat3 m0 data register 3 0x25 0x5 m0adr m0 address register 0x26 0x6 m0sc m0 status and configuration register 0x27 0x7 pfcd pfc data 0x28 0x8 pfcsc pfc status and command 0x29 0x9 mcpusel dmce select register 0x2a 0xa adcconf adc configuration 0x2b 0xb adcires adc interrupt reset (write only) adcd adc data (read only) 0x2c 0xc adcreq adc sample request (write only) adcint adc interrupts (read only) 0x2d 0xd portei porteo gpio port e data input/output 0x2e 0xe portee gpio port e output enable 0x2f 0xf ioexpa io expander address 0x30 0x10 srd0 shadow ram low byte of data 0x31 0x11 srd1 shadow ram high byte of data 0x32 0x12 sra0 shadow ram low byte of address 0x33 0x13 sra1 shadow ram high byte of address 0x34 0x14 srsc shadow ram status and command 0x35 0x15 portai portao gpio port a data input/output 0x36 0x16 portbi portbo gpio port b data input/output 0x37 0x17 portci portco gpio port c data input/output 0x38 0x18 portdi portdo gpio port d data input/output 0x39 0x19 portae gpio port a output enable 0x3a 0x1a portbe gpio port b output enable indirect 10 bit address direct 6 bit address register name comments page 0x3b 0x1b portce gpio port c output enable 0x3c 0x1c portde gpio port d output enable register 0x3d 0x1d portie gpio interrupt enable register 0x3e 0x1e portifr gpio interrupt flag indicator and reset register 0x3f 0x1f ioexpd io expander data 0x30 0x20 0x41 0x21 wdtcr watchdog timer control register 0x42 0x22 tcr0 timer 0 control register 0x43 0x23 tcnt0 timer 0 counter value register 0x44 0x24 ocr0 timer 0 output compare value register 0x45 0x25 tcr1 timer 1 control register 0x46 0x26 tcnt1 timer 1 counter value register 0x47 0x27 ocr1 timer 1 output compare value register 0x48 0x28 tcr2 timer 2 control register 0x49 0x29 tcntl2 timer 2 counter value register, low byte 0x4a 0x2a tcnth2 timer 2 counter value register, high byte 0x4b 0x2b ocrl2 timer 2 output compare value register, low byte 0x4c 0x2c ocrh2 timer 2 output compare value register, high byte 0x50 0x30 ucsr uart status and configuration register 0x51 0x31 rxb uart receive register 0x52 0x32 txb uart transmit register 0x53 0x33 intconl interrupt controller low configuration register 0x54 0x34 intconh interrupt controller high configuration register 0x55 0x35 twisc two wire interface status and configuration 0x56 0x36 twiadr two wire interface address 0x57 0x37 twidat two wire interface data 0x58 0x38 spictrl spi control register 0x59 0x39 spidat spi data register 0x5d 0x3d spl stack pointer low byte 0x5e 0x3e sph stack pointer high byte 0x5f 0x3f sreg mcu status register
AMG-XB404 fully integrated single motor controller for electrical motors 5.11. mcu instruction set flag description c carry flag z result is zero n result is negative v two's complement overflow indicator s n+v, used for signed tests h half carry flag t transfer bit used (bld and bst instructions) i global interrupt enable flag table 33 : mcu flags operand description rd destination register in register file rr source register in register file r result after instruction executed k constant data k constant address b bit in register file or io register s bit in status register x,y,z indirect address register (x={r27:r26}, y={r29:r28}, z={r31:r30}) a i/o location address q displacement for indirect addressing table 34 : mcu operands AMG-XB404 revision: a 2. nov. 2012 ? all rights reserved page 59 of 73
AMG-XB404 fully integrated single motor controller for electrical motors mnemonic operands description operation flags w n binary opcode arithmetic and logic instructions add rd, rr add two registers rd rd + rr 0 d 31; 0 r 31 z,c,n,v,h,s 1 1 0000 11rd dddd rrrr adc rd, rr add with carry two registers rd rd + rr + c 0 d 31; 0 r 31 z,c,n,v,h,s 1 1 0001 11rd dddd rrrr adiw rdl, k add immediate to word rdh:rdl rdh:rdl + k d = 24, 26, 28, 30; 0 k 63 z,c,n,v,s 1 1 1001 0110 kkdd kkkk sub rd, rr subtract two registers rd rd - rr 0 d 31; 0 r 31 z,c,n,v,h,s 1 1 0001 10rd dddd rrrr subi rd, k subtract constant from register rd rd C k 16 d 31; 0 k 255 z,c,n,v,h,s 1 1 0101 kkkk dddd kkkk sbc rd, rr subtract with carry two registers rd rd C rr - c 0 d 31; 0 r 31 z,c,n,v,h,s 1 1 0000 10rd dddd rrrr sbci rd, k subtract constant from register with carry rd rd C k - c 16 d 31; 0 k 255 z,c,n,v,h,s 1 1 0100 kkkk dddd kkkk sbiw rdl, k subtract immediate from word rdh:rdl rdh:rdl + k d = 24, 26, 28, 30; 0 k 63 z,c,n,v,s 1 1 1001 0111 kkdd kkkk and rd, rr logical and registers rd rd & rr 0 d 31; 0 r 31 z,n,v,s 1 1 0010 00rd dddd rrrr andi rd, k logical and register and constant rd rd & k 16 d 31; 0 k 255 z,n,v,s 1 1 0111 kkkk dddd kkkk or rd, rr logical or registers rd rd | rr 0 d 31; 0 r 31 z,n,v,s 1 1 0010 10rd dddd rrrr ori rd, k logical or register and constant rd rd | k 16 d 31; 0 k 255 z,n,v,s 1 1 0110 kkkk dddd kkkk eor rd, rr exclusive or registers rd rd ^ rr 0 d 31; 0 r 31 z,n,v,s 1 1 0010 01rd dddd rrrr com rd ones complement rd 8hff - rd 0 d 31 z,c,n,v,s 1 1 1001 010d dddd 0000 neg rd twos complement rd 8h00 - rd 0 d 31 z,c,n,v,h,s 1 1 1001 010d dddd 0001 sbr rd,k set bit(s) in register rd rd i k 16 d 31; 0 k 255 z,n,v,s 1 1 0110 kkkk dddd kkkk cbr rd,k clear bit(s) in register rd rd & (8hff - k) 16 d 31; 0 k 255 z,n,v,s 1 1 0110 !k!k!k!k dddd !k!k!k!k inc rd increment rd rd + 1 0 d 31 z,n,v,s 1 1 1001 010d dddd 0011 dec rd decrement rd rd - 1 0 d 31 z,n,v,s 1 1 1001 010d dddd 1010 tst rd test for zero or minus rd rd & rd 0 d 31 z,n,v,s 1 1 0010 00dd dddd dddd clr rd clear register rd rd ^ rd 0 d 31 z,n,v,s 1 1 0010 01dd dddd dddd ser rd set register rd 8hff 16 d 31 none 1 1 1110 1111 dddd 1111 mul rd, rr multiply unsigned r1:r0 rd * rr 0 d 31; 0 r 31 z,c 1 1 1001 11rd dddd rrrr muls rd, rr multiply signed r1:r0 rd * rr 16 d 31; 16 r 31 z,c 1 1 0000 0010 dddd rrrr mulsu rd, rr multiply signed with unsigned r1:r0 rd * rr 16 d 23; 16 r 23 z,c 1 1 0000 0011 0ddd 0rrr fmul rd, rr fractional multiply unsigned r1:r0 (rd * rr) << 1 16 d 23; 16 r 23 z,c 1 1 0000 0011 0ddd 1rrr fmuls rd, rr fractional multiply signed r1:r0 (rd * rr) << 1 16 d 23; 16 r 23 z,c 1 1 0000 0011 1ddd 0rrr AMG-XB404 revision: a 6. nov. 2012 ? all rights reserved page 60 of 73
AMG-XB404 fully integrated single motor controller for electrical motors mnemonic operands description operation flags w n binary opcode fmulsu rd, rr fractional signed by unsigned multiply r1:r0 (rd * rr) << 1 16 d 23; 16 r 23 z,c 1 1 0000 0011 1ddd 1rrr branch instructions rjmp k relative jump pc pc + k + 1 -2k k < 2k none 1 1 1100 kkkk kkkk kkkk ijmp k indirect jump to (z) pc z[12:0] none 1 1 1001 0100 0000 1001 jmp k direct jump pc k 0 k < 8k none 2 2 1001 010k kkkk 110k kkkk kkkk kkkk kkkk rcall k relative subroutine call pc pc + k + 1 -2k k < 2k none 1 2 1101 kkkk kkkk kkkk icall k indirect call to (z) pc z[12:0] none 1 2 1001 0101 0000 1001 call k direct subroutine call pc k 0 k < 2k none 2 2 1001 010k kkkk 111k kkkk kkkk kkkk kkkk ret subroutine return pc stack none 1 2 1001 0101 0000 1000 reti interrupt return pc stack none 1 2 1001 0101 0001 1000 cpse rd, rr compare, skip if equal if (rd = rr) pc pc + (2 or 3) 0 d 31; 0 r 31 none 1 1/2 0001 00rd dddd rrrr cp rd, rr compare rd - rr 0 d 31; 0 r 31 z,c,n,v,h,s 1 1 0001 01rd dddd rrrr cpc rd, rr compare with carry rd - rr - c 0 d 31; 0 r 31 z,c,n,v,h,s 1 1 0000 01rd dddd rrrr cpi rd, k compare register with immediate rd - k 16 d 31; 0 k 255 z,n,v,c,h,s 1 1 0011 kkkk dddd kkkk sbrc rr, b skip if bit in register cleared if (rr(b) = 0) pc pc + (2 or 3) 0 r 31; 0 b 7 none 1 1/2 1111 110r rrrr 0bbb sbrs rr, b skip if bit in register is set if (rr[b] = 1) pc pc + (2 or 3) 0 r 31; 0 b 7 none 1 1/2 1111 111r rrrr 0bbb sbic a, b skip if bit in i/o register cleared if (i/o(a,b) = 0) pc pc + (2 or 3) 0 a 31; 0 b 7 none 1 1/2 1001 1001 aaaa abbb sbis a, b skip if bit in i/o register is set if (i/o(a,b) = 1) pc pc + (2 or 3) 0 a 31; 0 b 7 none 1 1/2 1001 1011 aaaa abbb brbs s, k branch if status flag set if (sreg[s] = 1) pc pc + k + 1 0 s 7; -64 k 63 none 1 1 1111 00kk kkkk ksss brbc s, k branch if status flag cleared if (sreg[s] = 0) pc pc + k + 1 0 s 7; -64 k 63 none 1 1 1111 01kk kkkk ksss breq k branch if equal if (z = 1) pc pc + k + 1 -64 k 63 none 1 1 1111 00kk kkkk k001 brne k branch if not equal if (z = 0) pc pc + k + 1 -64 k 63 none 1 1 1111 01kk kkkk k001 brcs k branch if carry set if (c = 1) pc pc + k + 1 -64 k 63 none 1 1 1111 00kk kkkk k000 brcc k branch if carry cleared if (c = 0) pc pc + k + 1 -64 k 63 none 1 1 1111 01kk kkkk k000 brsh k branch if same or higher if (c = 0) pc pc + k + 1 -64 k 63 none 1 1 1111 01kk kkkk k000 brlo k branch if lower if (c = 1) pc pc + k + 1 -64 k 63 none 1 1 1111 00kk kkkk k000 brmi k branch if minus if (n = 1) pc pc + k + 1 -64 k 63 none 1 1 1111 00kk kkkk k010 brpl k branch if plus if (n = 0) pc pc + k + 1 -64 k 63 none 1 1 1111 01kk kkkk k010 AMG-XB404 revision: a 6. nov. 2012 ? all rights reserved page 61 of 73
AMG-XB404 fully integrated single motor controller for electrical motors mnemonic operands description operation flags w n binary opcode brge k branch if greater or equal, signed if (s = 0) pc pc + k + 1 -64 k 63 none 1 1 1111 01kk kkkk k100 brlt k branch if less than zero, signed if (s = 1) pc pc + k + 1 -64 k 63 none 1 1 1111 00kk kkkk k100 brhs k branch if half carry flag set if (h = 1) pc pc + k + 1 -64 k 63 none 1 1 1111 00kk kkkk k101 brhc k branch if half carry flag cleared if (h = 0) pc pc + k + 1 -64 k 63 none 1 1 1111 01kk kkkk k101 brts k branch if t flag set if (t = 1) pc pc + k + 1 -64 k 63 none 1 1 1111 00kk kkkk k110 brtc k branch if t flag cleared if (t = 0) pc pc + k + 1 -64 k 63 none 1 1 1111 01kk kkkk k110 brvs k branch if overflow flag set if (v = 1) pc pc + k + 1 -64 k 63 none 1 1 1111 00kk kkkk k011 brvc k branch if overflow flag cleared if (v = 0) pc pc + k + 1 -64 k 63 none 1 1 1111 01kk kkkk k011 brie k branch if interrupt enabled if (i = 1) pc pc + k + 1 -64 k 63 none 1 1 1111 00kk kkkk k111 brid k branch if interrupt disabled if (i = 0) pc pc + k + 1 -64 k 63 none 1 1 1111 01kk kkkk k111 data transfer instructions mov rd, rr move between registers rd rr 0 d 31; 0 r 31 none 1 1 0010 11rd dddd rrrr movw rd, rr copy register word rd+1:rd rr+1:rr d = 0, 2...30; r = 0, 2...30 none 1 1 0000 0001 dddd rrrr ldi rd, k load immediate rd k 16 d 31; 0 k 255 none 1 1 1110 kkkk dddd kkkk ld rd, x load indirect rd (x) 0 d 31 none 1 1 1001 000d dddd 1100 ld rd, x+ load indirect and post-increment rd (x), x x + 1 0 d 31 none 1 1 1001 000d dddd 1101 ld rd, -x load indirect and pre-decrement x x - 1, rd (x) 0 d 31 none 1 1 1001 000d dddd 1110 ld rd, y load indirect rd (y) 0 d 31 none 1 1 1000 000d dddd 1000 ld rd, y+ load indirect and post-increment rd (y), y y + 1 0 d 31 none 1 1 1001 000d dddd 1001 ld rd, -y load indirect and pre-decrement y y - 1, rd (y) 0 d 31 none 1 1 1001 000d dddd 1010 ldd rd, y+q load indirect with displacement rd (y + q) 0 d 31 0 q 63 none 1 1 10q0 qq0d dddd 1qqq ld rd, z load indirect rd (z) 0 d 31 none 1 1 1000 000d dddd 0000 ld rd, z+ load indirect and post-increment rd (z), z z + 1 0 d 31 none 1 1 1001 000d dddd 0001 ld rd, -z load indirect and pre-decrement z z - 1, rd (z) 0 d 31 none 1 1 1001 000d dddd 0010 ldd rd, z+q load indirect with displacement rd (z + q) 0 d 31 0 q 63 none 1 1 10q0 qq0d dddd 0qqq lds rd, k load direct from sram rd (k) 0 d 31 0 k 607 none 2 2 1001 000d dddd 0000 kkkk kkkk kkkk kkkk st x, rr store indirect (x) rr 0 r 31 none 1 1 1001 001r rrrr 1100 AMG-XB404 revision: a 6. nov. 2012 ? all rights reserved page 62 of 73
AMG-XB404 fully integrated single motor controller for electrical motors mnemonic operands description operation flags w n binary opcode st x+, rr store indirect and post-increment (x) rr, x x + 1 0 r 31 none 1 1 1001 001r rrrr 1101 st -x, rr store indirect and pre-decrement x x C 1, (x) rr 0 r 31 none 1 1 1001 001r rrrr 1110 st y, rr store indirect (y) rr 0 r 31 none 1 1 1000 001r rrrr 1000 st y+, rr store indirect and post-increment (y) rr, y y + 1 0 r 31 none 1 1 1001 001r rrrr 1001 st -y, rr store indirect and pre-decrement y y C 1, (y) rr 0 r 31 none 1 1 1001 001r rrrr 1010 std y+q, rr store indirect with displacement (y + d) rr 0 r 31 0 q 63 none 1 1 10q0 qq1r rrrr 1qqq st z, rr store indirect (z) rr 0 r 31 none 1 1 1000 001r rrrr 0000 st z+, rr store indirect and post-increment (z) rr, z z + 1 0 r 31 none 1 1 1001 001r rrrr 0001 st -z, rr store indirect and pre-decrement z z C 1, (z) rr 0 r 31 none 1 1 1001 001r rrrr 0010 std z+q, rr store indirect with displacement (z + d) rr 0 r 31 0 q 63 none 1 1 10q0 qq1r rrrr 0qqq sts k,rr store direct to data space (k) rr 0 d 31 0 k 607 none 2 2 1001 001d dddd 0000 kkkk kkkk kkkk kkkk lpm load program memory r0 (z) none 1 2 1001 0101 1100 1000 lpm rd, z load program memory rd (z) 0 d 31 none 1 2 1001 000d dddd 0100 lpm rd, z+ load program memory and post-increment rd (z) 0 d 31 none 1 2 1001 000d dddd 0101 in rd, a io port in rd i/o(a) 0 d 31 0 a 63 none 1 1 1011 0aad dddd aaaa out a, rr io port out i/o(a) rr 0 d 31 0 a 63 none 1 1 1011 1aar rrrr aaaa push rr push register on stack stack rr 0 r 31 none 1 1 1001 001d dddd 1111 pop rd pop register from stack rd stack 0 d 31 none 1 1 1001 000d dddd 1111 bit and bit-test instructions sbi a, b set bit in i/o register i/o(a,b) 1 0 a 31 0 b 7 none 1 1 1001 1010 aaaa abbb cbi a, b clear bit in i/o register i/o(a,b) 0 0 a 31 0 b 7 none 1 1 1001 1000 aaaa abbb lsl rd logical shift left rd[n+1] rd[n], c rd[7], rd[0] 0 0 d 31 z,c,n,v,h,s 1 1 0000 11dd dddd dddd lsr rd logical shift right rd[n] rd[n+1], c rd[0], rd[7] 0 0 d 31 z,c,n,v,s 1 1 1001 010d dddd 0110 rol rd rotate left through carry rd[0] c, rd(n+1) rd[n], c rd[7] 0 d 31 z,c,n,v,h,s 1 1 0001 11dd dddd dddd ror rd rotate right through carry rd[7] c, rd[n] rd[n+1], c rd[0] 0 d 31 z,c,n,v,s 1 1 1001 010d dddd 0111 AMG-XB404 revision: a 6. nov. 2012 ? all rights reserved page 63 of 73
AMG-XB404 fully integrated single motor controller for electrical motors mnemonic operands description operation flags w n binary opcode asr rd arithmetic shift right c rd[0], rd[n] rd[n+1], rd[7] rd[7] 0 d 31 z,c,n,v,s 1 1 1001 010d dddd 0101 swap rd swap nibbles rd[3:0] rd[7:4], rd[7:4] rd[3:0] 0 d 31 none 1 1 1001 010d dddd 0010 bset s flag set sreg[s] 1 0 s 7 sreg[s] 1 1 1001 0100 0sss 1000 bclr s flag clear sreg[s] 0 0 s 7 sreg[s] 1 1 1001 0100 1sss 1000 bst rr, b store bit from register to t t rr[b] 0 r 31 0 b 7 t 1 1 1111 101d dddd 0bbb bld rd, b load bit from t to register rd[b] t 0 r 31 0 b 7 none 1 1 1111 100d dddd 0bbb sec set carry c 1 c 1 1 1001 0100 0000 1000 clc clear carry c 0 c 1 1 1001 0100 1000 1000 sen set negative flag n 1 n 1 1 1001 0100 0010 1000 cln clear negative flag n 0 n 1 1 1001 0100 1010 1000 sez set zero flag z 1 z 1 1 1001 0100 0001 1000 clz clear zero flag z 0 z 1 1 1001 0100 1001 1000 sei global interrupt enable n 1 i 1 1 1001 0100 0111 1000 cli global interrupt disable n 0 i 1 1 1001 0100 1111 1000 ses set signed test flag s 1 s 1 1 1001 0100 0100 1000 cls clear signed test flag s 0 s 1 1 1001 0100 1100 1000 sev set twos complement overflow v 1 v 1 1 1001 0100 0011 1000 clv clear twos complement overflow v 0 v 1 1 1001 0100 1011 1000 set set t in sreg t 1 t 1 1 1001 0100 0110 1000 clt clear t in sreg t 0 t 1 1 1001 0100 1110 1000 seh set half carry flag in sreg h 1 h 1 1 1001 0100 0101 1000 clh clear half carry flag in sreg h 0 h 1 1 1001 0100 1101 1000 mcu control instructions nop no operation none 1 1 0000 0000 0000 0000 sleep sleep none 1 1 1001 0101 1000 1000 wdr watchdog reset none 1 1 1001 0101 1010 1000 table 35 : mcu instruction set, w denotes number of program words, n denotes number of clock cycles AMG-XB404 revision: a 6. nov. 2012 ? all rights reserved page 64 of 73
AMG-XB404 fully integrated single motor controller for electrical motors 6. pinning . pin # symbol description pin # symbol description 1 pc6/ spi_di mcu portc pin 6 gpio 33 m0r3 m0 phase return input 3 2 pc7/ spi_clk mcu portc pin 7 gpio 34 xo crystal oscillator input 3 clkio clock input/output 35 xo_osel crystal oscillator input / osc select 4 dgnd1 digital gnd 36 npor power on reset monitor (output) 5 dgnd2 digital gnd 37 pfc_pwm pfc pwm output 6 nresin reset input 38 m0ofi m0 over current input 7 nresout reset output 39 m0o1 m0 gate driver output 1 8 clksel clock select 40 m0o2 m0 gate driver output 2 9 swv smps voltage sense input 41 m0o3 m0 gate driver output 3 10 swvfb smps voltage sense feedback 42 m0o4 m0 gate driver output 4 11 swdrv smps gate driver output 43 m0o5 m0 gate driver output 5 12 swi smps current sense input 44 m0o6 m0 gate driver output 6 13 swvdd smps supply voltage input 45 dvdd1 2.5v digital supply voltage 14 swvref smps reference voltage 46 d5v1 digital 5v input 15 dgnd3 digital gnd 47 pb0/ uart_tx mcu portb pin 0 gpio 16 adc0 adc input channel mcu porte pin 0 gpio 48 pb1/ uart_rx mcu portb pin 1 gpio 17 adc1 adc input channel mcu porte pin 1 gpio 49 pb2/ iic_sclk mcu portb pin 2 gpio 18 adc2 adc input channel mcu porte pin 2 gpio 50 pb3/ iic_sda mcu portb pin 3 gpio 19 dvdd2 2.5v digital supply voltage 51 pb4/ t0_out mcu portb pin 4 gpio 20 d5v2 digital 5v input 52 pb5/ t1_out mcu portb pin 5 gpio 21 vdc pfc dc bus voltage input 53 pb6/ t2_out mcu portb pin 6 gpio 22 vac pfc rectified ac voltage input 54 pb7 mcu portb pin 7 gpio 23 vref adc reference voltage 55 sdi spi unit serial data input 24 agnd analog gnd 56 sdo spi unit serial data output 25 avdd 2.5v analog voltage output 57 scs spi unit chip select input 26 a5v analog 5v input 58 sclk spi unit clock input AMG-XB404 revision: a 2. nov. 2012 ? all rights reserved page 65 of 73
AMG-XB404 fully integrated single motor controller for electrical motors pin # symbol description pin # symbol description 27 pfci pfc ac current sense input 59 dvdd3 2.5v digital supply voltage 28 pfcifb pfc ac current sense feedback 60 d5v3 digital 5v input 29 m0i m0 current sense input 61 pc2/t2_in mcu portc pin 2 gpio 30 m0ifb m0 current sense feedback 62 pc3 mcu portc pin 3 gpio 31 m0r1 m0 phase return input 1 63 pc4/spi_ cs mcu portc pin 4 gpio 32 m0r2 m0 phase return input 2 64 pc5/spi_ do mcu portc pin 5 gpio table 36 : AMG-XB404 pin list 7. absolute maximum ratings the absolute maximum ratings may not be exceeded under any circumstances. # symbol parameter min max unit 1 v in voltage on any analog or digital signal pin -0.3 v vdd +0.3v v 2 v swdrv voltage on switching supply driver output swdrv -0.3 v swvdd +0.3 v 3 v swvdd voltage on switching supply pin swvdd -0.3 6 v 4 v d5v voltage on digital supply pin d5vx v swvdd - 0.3 v swvdd + 0.3 v 5 v a5v voltage on analog supply pin a5v -0.3 6 6 v agnd voltage on analog ground pin agnd -0.3 0.5 v 7 v vd voltage on digital supply pin dvddx -0.3 2.75 v 8 v vref voltage on analog reference voltage pin vref -0.3 2.75 v 9 i out logic output current -20 20 ma 10 v esd esd protection voltage (all pins) -1 1 kv 11 t stb storage temperature before programming -40 125 c 12 t sta storage temperature after programming -40 85 c 13 t j junction temperature 125 c table 37 : AMG-XB404 absolute maximum ratings AMG-XB404 revision: a 2. nov. 2012 ? all rights reserved page 66 of 73
AMG-XB404 fully integrated single motor controller for electrical motors 8. electrical characteristics unless otherwise specified, the minimum and maximum characteristics contain the spread of values guaranteed within the specified operating conditions. unless otherwise specified, typical values are given with d5v = a5a = 5v , t a = 25c 8.1. operational range # symbol parameter min typ max unit 1 v swvdd voltage on switching supply pin swvdd 4.3 5.5 v 2 v d5v voltage on general supply pin d5v 4.5 5.0 5.5 v 3 v agnd voltage on analog ground pin agnd -0.1 0 0.1 v 4 v inh logic high signal input voltage [v d5v =5v] 1.7 5.3 v 5 v inl logic low signal input voltage [v d5v =5v] 0 0.8 v 6 t a ambient operating temperature -25 25 85 3 c 7 r th package thermal resistance 40 k/w table 38 : AMG-XB404 operational range 8.2. dc characteristics # symbol parameter min typ max unit 1 v vref voltage on analog reference pin vref 1.62 1.8 1.98 v 2 v vcc voltage on analog supply pin avdd 2.25 2.5 2.75 v 3 v vd voltage on logic core supply pin dvddx 2.25 2.5 2.75 v 4 v swvref voltage on switching supply reference pin swvref 1.29 v 5 v vswdrv high voltage on switching supply driver pin swdrv [i vswdrv =20ma] 3.5 v swvdd v 6 v por power-on reset voltage 3.8 4.1 4.4 v 7 v bo brown-out voltage 3.3 3.6 3.9 v 8 n temp temperature channel resolution 0.625 k/bit 9 n vdd voltage channel resolution 8 mv/bit table 39 : AMG-XB404 dc characteristics 3 the junction temperature is given as a chip temperature which depends on the ic's total power dissipation. the junction temperature can be calculated as t j = t a r th ? p tot , where p tot denotes the total power dissipation. AMG-XB404 revision: a 2. nov. 2012 ? all rights reserved page 67 of 73
AMG-XB404 fully integrated single motor controller for electrical motors 8.3. ac characteristics # symbol parameter min typ max unit 1 f clki internal rc-oscillator frequency 175 350 500 khz 2 d f internal rc-oscillator frequency deviation -2 +2 % 3 f in initial fll frequency 22.5 45 64 mhz 4 t por power-on reset delay time [after d5v 0v5v step] 5 ms 5 t lock fll reset delay time 10 ms 6 f sw switching supply frequency (rc oscillator) [start up, before setting divider] 10 22 35 khz 7 f scl eeprom clock frequency, scl 1000 khz 8 t low eeprom clock pulse width low 0.4 s 9 t high eeprom clock pulse width high 0.4 s 10 t aa eeprom clock low to data out valid 0.05 0.55 s 11 t hd.sta eeprom start hold time 0.25 s 12 t su.sta eeprom start setup time 0.25 s 13 t hd.dat eeprom data in hold time 0 s 14 t su.dat eeprom data in setup time 0.1 s 15 t r eeprom inputs rise time 0.3 s 16 t f eeprom inputs fall time 0.1 s 17 t su.sto eeprom stop setup time 0.25 s 18 t dh eeprom data out hold time 50 ns 19 t wr eeprom write cycle time 5 ms table 40 : AMG-XB404 ac characteristics 8.4. adc characteristics # symbol parameter min typ max unit 1 n a resolution - 10 - bit 2 f adc conversion rate - 2 - msmp/s 3 inl 4 integral non-linearity 0.5 % fsr 5 4 o ffset offset 1 lsb table 41 : AMG-XB404 adc characteristics 4 absolute linearity is guaranteed by design 5 full scale range AMG-XB404 revision: a 2. nov. 2012 ? all rights reserved page 68 of 73
AMG-XB404 fully integrated single motor controller for electrical motors 8.5. supply current characteristics # symbol parameter min typ max unit 1 i d5v_sleep idle mode digital supply current [f fll =64mhz, all units off] 40 ma 2 i d5v_op operating mode digital supply current [f fll =64mhz, all units on] 60 90 ma 3 i a5v_sleep quiescent analog supply current [f fll =64mhz, bias off] 1.2 ma 4 i a5v_op operating analog supply current [f fll =64mhz, all amplifiers enabled] 7.7 12 ma 5 i swvddq switching controller quiescent supply current [v swvdd =3.5v] 130 a i swvddo switching controller operating supply current [v swvdd =5v] 0.7 1.2 ma table 42 : AMG-XB404 supply current characteristics 8.6. logic-level characteristics # symbol parameter min typ max unit 1 i in,h logic high signal input current -0.1 0.1 a 2 -i in,l logic low signal input current -0.1 0.1 a 3 v out,h logic high signal output voltage [i out =-15ma, v d5v =5v] 4 4.7 v 4 v out,l logic low signal output voltage [i out =15 ma, v d5v =5v] 0.2 0.8 v table 43 : AMG-XB404 logic-level characteristics AMG-XB404 revision: a 2. nov. 2012 ? all rights reserved page 69 of 73
AMG-XB404 fully integrated single motor controller for electrical motors 9. ic-package ? package: lqfp68 C body size: 10 mm x 10 mm x 1.4mm, rohs compliant ? termal resistance: r th = 40 k/w figure 41 : lqfp package drawing AMG-XB404 revision: a 2. nov. 2012 ? all rights reserved page 70 of 73
AMG-XB404 fully integrated single motor controller for electrical motors notes: 1. dimensions d1 and e1 do not include mold protrusion. allowable protrusion is 0.25 [.010] per side. d1 and e1 are maximum plastic body size dimensions including mold mismatch 2. the top package body size may be smaller than the bottom body size by as much as 0.15 [.006] 3. drawing conforms to jedec ms-026 rev. d 4. controlling dimensions in mm symbol min typ max d 11.8 12.0 12.2 .464 .472 .480 d1 9.9 10.0 10.1 .390 .394 .398 e 11.8 12.0 12.2 .464 .472 .480 e1 9.9 10.0 10.1 .390 .394 .398 b 0.17 0.22 0.27 .007 .009 .011 b1 0.17 0.20 0.23 .007 .008 .009 c 0.09 0.20 .004 .008 c1 0.09 0.16 .004 .006 e 0.50 .020 ccc 0.08 .003 ddd 0.08 .003 n 64 table 44 : lqfp64 package dimensions 10. ic-marking xb404 11. packing specification ? ic in tray (esd bag, vacuum sealed, max. 10 trays per bag) ? 160 ics per tray AMG-XB404 revision: a 2. nov. 2012 ? all rights reserved page 71 of 73 yyww ****** date code lot number top marking by laser
AMG-XB404 fully integrated single motor controller for electrical motors 12. notes and cautions 12.1. esd protection the requirements for handling electrostatic discharge sensitive devices are described in the jedec standard jesd625-a. please note the following recommendations: ? when handling the device, operators must be grounded by wearing a for the purpose designed grounded wrist strap with at least 1m resistance and direct skin contact. ? operators must at all times wear esd protective shoes or the area should be surrounded by for esd protection intended floor mats. ? opening of the protective esd package that the device is delivered in must only occur at a properly equipped esd workbench. the tape with which the package is held together must be cut with a sharp cutting tool, never pulled or ripped off. ? any unnecessary contact with the device or any unprotected conductive points should be avoided. ? work only with qualified and grounded tools, measuring equipment, casing and workbenches. ? outside properly protected esd-areas the device or any electronic assembly that it may be part of should always be transported in egb/esd shielded packaging. 12.2. storage conditions the AMG-XB404 corresponds to moisture sensitivity classification msl2 , according to jedec standard j-std-020, and should be handled and stored according to j-std-033. 13. disclaimer information given in this data sheet is believed to be accurate and reliable. however, no responsibility is assumed for the consequences of its use nor for any infringement of patents or other rights of third parties that may result from its use. alpha microelectronics gmbh does not authorize or warrant any of its products for use in life support system equipment. the values stated in absolute maximum ratings may under no circumstances be exceeded. no warranty is given for use in life support systems or medical equipment without the specific written consent of alpha microelectronics gmbh. for questions regarding the application please contact the publisher. the declared data are only a description of the product. they are not guaranteed properties as defined by law. examples are given without obligations and cannot give rise to any liability. reprinting of this data sheet C or any part of it C is not allowed without the license of the publisher. data sheets are subject to change without any notice. AMG-XB404 revision: a 2. nov. 2012 ? all rights reserved page 72 of 73
AMG-XB404 fully integrated single motor controller for electrical motors 14. contact information this data sheet is published by alpha microelectronics gmbh. to order samples or inquire information please contact: alpha microelectronics gmbh im technologiepark 1 15236 frankfurt (oder) germany am.info@alpha-microelectronics.de www.alpha-microelectronics.de +49-335-557-1750 (telephone) +49-335-557-1759 (fax) ? all rights reserved. AMG-XB404 revision: a 2. nov. 2012 ? all rights reserved page 73 of 73

▲Up To Search▲

Price & Availability of AMG-XB404

	To Download AMG-XB404 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .